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Pull requests: enjoy-digital/litex
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build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
#2123
opened Nov 9, 2024 by
trabucayre
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Fixes: Fix no close trace file when the sim is finished
#2120
opened Nov 7, 2024 by
juiceRv
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Utilizing all available CPU cores in the software make cmd
#2119
opened Nov 6, 2024 by
long-pham
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Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl
#2117
opened Nov 6, 2024 by
long-pham
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Add "--depth" and "-b" arguments for git clone command
#2116
opened Nov 6, 2024 by
John-Tito
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Optimize Build, Enhance Clock Control, and add FTDI serial number option to openfpgaloader
#2111
opened Oct 31, 2024 by
long-pham
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build: io: add multibit/bus variants of SDR and DDR
#2105
opened Oct 25, 2024 by
maass-hamburg
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build: efinix: allow clk inverting and different in clk on reg tristates
#2087
opened Oct 1, 2024 by
maass-hamburg
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Fix AXI version of the Zynq7000 busses and add mapped connect fuction
answered-waiting-feedback
#1989
opened Jun 16, 2024 by
JoyBed
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