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Merge branch 'master' into fix-rfdiv-macro
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jerzyjamroz authored Oct 12, 2023
2 parents 544fddd + 5599ea6 commit 9654d08
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5 changes: 5 additions & 0 deletions .github/CODEOWNERS
Validating CODEOWNERS rules …
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
# See https://help.github.com/articles/about-codeowners/ for valid syntax for entries.

# Sets the relevant support.
evm-mtca-300*.substitutions @jerzyjamroz
evr-300.substitutions @jerzyjamroz
23 changes: 6 additions & 17 deletions .github/workflows/ci-scripts-build.yml
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ on:
- 'documentation/**'
- 'python/**'
- '**/*.md'
workflow_dispatch:

env:
SETUP_PATH: .ci-local:.ci
Expand Down Expand Up @@ -68,11 +69,6 @@ jobs:
base: "7.0"
extra: "CMD_CXXFLAGS=-std=c++11"

- os: ubuntu-16.04
cmp: clang
configuration: default
base: "7.0"

- os: ubuntu-20.04
cmp: clang
configuration: default
Expand All @@ -91,18 +87,6 @@ jobs:
base: "7.0"
rtems: "4.9"

- os: ubuntu-16.04
cmp: gcc-4.8
utoolchain: "4.8"
configuration: default
base: "7.0"

- os: ubuntu-16.04
cmp: gcc-4.9
utoolchain: "4.9"
configuration: default
base: "7.0"

- os: ubuntu-20.04
cmp: gcc-8
utoolchain: "8"
Expand All @@ -114,6 +98,11 @@ jobs:
configuration: default
base: "7.0"

- os: ubuntu-latest
cmp: gcc
configuration: default
base: "7.0"

steps:
- uses: actions/checkout@v2
with:
Expand Down
13 changes: 13 additions & 0 deletions .github/workflows/doxygen-gh-pages.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
name: Doxygen GitHub Pages Deploy Action

on:
workflow_dispatch:

jobs:
deploy:
runs-on: ubuntu-latest
steps:
- uses: DenverCoder1/doxygen-github-pages-action@v1.3.0
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
folder: documentation/html
23 changes: 13 additions & 10 deletions .github/workflows/linux-build.yml
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ on:
pull_request:
paths:
- 'mrmShared/linux/**'
workflow_dispatch:

jobs:
specific:
Expand All @@ -20,23 +21,18 @@ jobs:
fail-fast: false
matrix:
include:
- os: ubuntu-16.04
series: 3.x
version: 3.2.1
cc: gcc-4.8

- os: ubuntu-16.04
series: 3.x
version: 3.16.1
cc: gcc-4.8

- os: ubuntu-20.04
series: 4.x
version: 4.9.1

- os: ubuntu-20.04
series: 5.x
version: 5.9.6

- os: ubuntu-latest
series: latest
version: latest

steps:
- uses: actions/checkout@v2
- name: Info
Expand All @@ -51,6 +47,13 @@ jobs:
- name: Setup Linux
run: |
install -d kernel
if [ "$KSER" == "latest" ]; then
KSER=$(curl -s https://cdn.kernel.org/pub/linux/kernel/ | grep -o 'v[0-9]\+\.[0-9a-zA-Z]\+/' | sed 's/\/\s*//' | sort -t. -k2,2V -k3,3V -k4,4V | tail -n 1 | sed 's/v//')
fi
if [ "$KVER" == "latest" ]; then
KVER=$(curl -s https://cdn.kernel.org/pub/linux/kernel/v$KSER/ | grep -o 'linux-[0-9]\+\.[0-9]\+\.[0-9]\+\.tar\.xz' | sort -t- -k2,2n -k3,3n -k4,4n | tail -n 1 | sed 's/linux-\(.*\)\.tar\.xz/\1/')
fi
echo "https://cdn.kernel.org/pub/linux/kernel/v$KSER/linux-$KVER.tar.xz"
curl -s https://cdn.kernel.org/pub/linux/kernel/v$KSER/linux-$KVER.tar.xz | tar -C kernel --strip-components=1 -xJ
make -C kernel CC=${CC:=gcc} defconfig
make -C kernel CC=${CC:=gcc} modules_prepare
Expand Down
30 changes: 9 additions & 21 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,14 +1,15 @@
What is Available?
------------------
* [![Docs](https://github.com/epics-modules/mrfioc2/actions/workflows/doxygen-gh-pages.yml/badge.svg)](https://github.com/epics-modules/mrfioc2/actions/workflows/doxygen-gh-pages.yml)
* [![EPICS driver](https://github.com/epics-modules/mrfioc2/actions/workflows/ci-scripts-build.yml/badge.svg)](https://github.com/epics-modules/mrfioc2/actions/workflows/ci-scripts-build.yml)
* [![Kernel module](https://github.com/epics-modules/mrfioc2/actions/workflows/linux-build.yml/badge.svg)](https://github.com/epics-modules/mrfioc2/actions/workflows/linux-build.yml)

More infomation on the Micro Research hardware can be found on their
website http://www.mrf.fi/.
---

Documentation appears at [http://epics.sourceforge.net/mrfioc2](http://epics.sourceforge.net/mrfioc2)
What is Available?
------------------

The latest developments can be found in the 'mrfioc2' VCS repository.
* More infomation on the Micro Research hardware can be found on their website http://www.mrf.fi/.

[https://github.com/epics-modules/mrfioc2](https://github.com/epics-modules/mrfioc2)
* Documentation at [http://epics.sourceforge.net/mrfioc2](http://epics.sourceforge.net/mrfioc2)

Prerequisites
-------------
Expand All @@ -19,17 +20,4 @@ Base: [http://www.aps.anl.gov/epics/base/R3-15/index.php](http://www.aps.anl.gov

devLib2: [https://github.com/epics-modules/devlib2/](https://github.com/epics-modules/devlib2/)

MSI (Base < 3.15 only): [http://www.aps.anl.gov/epics/extensions/msi/index.php](http://www.aps.anl.gov/epics/extensions/msi/index.php)

The Source
----------

VCS Checkout

```shell
git clone https://github.com/epics-modules/mrfioc2.git
```

Edit 'configure/CONFIG_SITE' and run "make".

<a href="https://travis-ci.org/epics-modules/mrfioc2"><img src="https://travis-ci.org/epics-modules/mrfioc2.svg">CI Build Status</img></a>
MSI: [http://www.aps.anl.gov/epics/extensions/msi/index.php](http://www.aps.anl.gov/epics/extensions/msi/index.php)
5 changes: 4 additions & 1 deletion evgMrmApp/Db/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,10 @@ DB += cpci-evg-300.db
DB += vme-evg230.db
DB += vme-evg230-nsls2.db
DB += mtca-evm-300.db
ifeq ($(shell echo "$(BASE) > 3.14" | bc),1)
DB += evm-mtca-300.db
DB += evm-mtca-300-evr.db
endif

ifneq ($(DEVIOCSTATS),)
ifeq ($(OS_CLASS), RTEMS)
Expand All @@ -47,4 +51,3 @@ USR_DBFLAGS += -I . -I .. -I $(INSTALL_LOCATION)/db
include $(TOP)/configure/RULES
#----------------------------------------
# ADD RULES AFTER THIS LINE

24 changes: 12 additions & 12 deletions evgMrmApp/Db/evgDbus.db
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ record(mbbiDirect, "$(P)Src-MbbiDir_") {
field( INP, "$(P)Src-Sel.RVAL CP")
}

record(bo, "$(P)Src:FrontInp0-Sel") {
record(bo, "$(P)Src$(s=:)FrontInp0-Sel") {
field( DESC, "Front Input0 on Dbus")
field( DTYP, "EVG Dbus")
field( OUT , "#C0 S$(dbusBit) @$(EVG):FrontInp0")
Expand All @@ -107,7 +107,7 @@ record(bo, "$(P)Src:FrontInp0-Sel") {
field( DOL, "$(P)Src-MbbiDir_.B0 CP")
}

record(bo, "$(P)Src:FrontInp1-Sel") {
record(bo, "$(P)Src$(s=:)FrontInp1-Sel") {
field( DESC, "Front Input1 on Dbus")
field( DTYP, "EVG Dbus")
field( OUT , "#C0 S$(dbusBit) @$(EVG):FrontInp1")
Expand All @@ -117,7 +117,7 @@ record(bo, "$(P)Src:FrontInp1-Sel") {
field( DOL, "$(P)Src-MbbiDir_.B1 CP")
}

record(bo, "$(P)Src:UnivInp0-Sel") {
record(bo, "$(P)Src$(s=:)UnivInp0-Sel") {
field( DESC, "Front Univ Input0 on Dbus")
field( DTYP, "EVG Dbus")
field( OUT , "#C0 S$(dbusBit) @$(EVG):UnivInp0")
Expand All @@ -127,7 +127,7 @@ record(bo, "$(P)Src:UnivInp0-Sel") {
field( DOL, "$(P)Src-MbbiDir_.B2 CP")
}

record(bo, "$(P)Src:UnivInp1-Sel") {
record(bo, "$(P)Src$(s=:)UnivInp1-Sel") {
field( DESC, "Front Univ Input1 on Dbus")
field( DTYP, "EVG Dbus")
field( OUT , "#C0 S$(dbusBit) @$(EVG):UnivInp1")
Expand All @@ -137,7 +137,7 @@ record(bo, "$(P)Src:UnivInp1-Sel") {
field( DOL, "$(P)Src-MbbiDir_.B3 CP")
}

record(bo, "$(P)Src:UnivInp2-Sel") {
record(bo, "$(P)Src$(s=:)UnivInp2-Sel") {
field( DESC, "Front Univ Input2 on Dbus")
field( DTYP, "EVG Dbus")
field( OUT , "#C0 S$(dbusBit) @$(EVG):UnivInp2")
Expand All @@ -147,7 +147,7 @@ record(bo, "$(P)Src:UnivInp2-Sel") {
field( DOL, "$(P)Src-MbbiDir_.B4 CP")
}

record(bo, "$(P)Src:UnivInp3-Sel") {
record(bo, "$(P)Src$(s=:)UnivInp3-Sel") {
field( DESC, "Front Univ Input3 on Dbus")
field( DTYP, "EVG Dbus")
field( OUT , "#C0 S$(dbusBit) @$(EVG):UnivInp3")
Expand All @@ -168,12 +168,12 @@ record(dfanout, "$(P)Omsl-FOut") {
field( VAL, "1")
field( UDF, "0")
field( OMSL, "supervisory")
field( OUTA, "$(P)Src:FrontInp0-Sel.OMSL")
field( OUTB, "$(P)Src:FrontInp1-Sel.OMSL")
field( OUTC, "$(P)Src:UnivInp0-Sel.OMSL")
field( OUTD, "$(P)Src:UnivInp1-Sel.OMSL")
field( OUTE, "$(P)Src:UnivInp2-Sel.OMSL")
field( OUTF, "$(P)Src:UnivInp3-Sel.OMSL")
field( OUTA, "$(P)Src$(s=:)FrontInp0-Sel.OMSL")
field( OUTB, "$(P)Src$(s=:)FrontInp1-Sel.OMSL")
field( OUTC, "$(P)Src$(s=:)UnivInp0-Sel.OMSL")
field( OUTD, "$(P)Src$(s=:)UnivInp1-Sel.OMSL")
field( OUTE, "$(P)Src$(s=:)UnivInp2-Sel.OMSL")
field( OUTF, "$(P)Src$(s=:)UnivInp3-Sel.OMSL")
info( autosaveFields_pass0, "VAL")
}

Expand Down
2 changes: 1 addition & 1 deletion evgMrmApp/Db/evgInput.db
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ record(bo, "$(P)EnaIrq-Sel") {
field( ONAM, "Enabled")
field( OMSL, "closed_loop")
# see evgMrm.db
field( DOL, "$(SYS){$(D)}1ppsInp-MbbiDir_.B$(Num) CP")
field( DOL, "$(PP=$(SYS){$(D)})1ppsInp-MbbiDir_.B$(Num) CP")
field( FLNK, "$(P)EnaIrq-RB")
info( autosaveFields_pass0, "VAL")
}
Expand Down
4 changes: 2 additions & 2 deletions evgMrmApp/Db/evgMxc.db
Original file line number Diff line number Diff line change
Expand Up @@ -68,14 +68,14 @@ record(longin , "$(P)Prescaler-RB") {
field( DTYP, "Obj Prop uint32")
field( INP , "@OBJ=$(OBJ), PROP=Prescaler")
field( DESC, "EVG Mux Prescaler RB")
field( FLNK, "$(SYS){$(D)}ResetMxc-Cmd")
field( FLNK, "$(PP=$(SYS){$(D)})ResetMxc-Cmd")
}

#
# When Evt Clock Frequency changes, Mxc Freq changes keeping the Prescaler same.
#
record(ai, "$(P)EvtClkFreq-RB_") {
field( INP, "$(SYS){$(D)-EvtClk}Frequency-RB CP")
field( INP, "$(PP=$(SYS){$(D)-)EvtClk$(s=})Frequency-RB CP")
field( FLNK, "$(P)Frequency-RB")
}

Expand Down
16 changes: 8 additions & 8 deletions evgMrmApp/Db/evgSoftSeq.template
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# linked from mrmSoftSeq.template
# $(P)InitSeq:Cont-FOut_
record(fanout, "$(P)TrigSrc:Init-FOut_") {
# $(P)InitSeq$(s=:)Cont-FOut_
record(fanout, "$(P)TrigSrc$(s=:)Init-FOut_") {
field( LNK1, "$(P)TrigSrc-Sel_")
}

Expand Down Expand Up @@ -41,10 +41,10 @@ record(mbbo, "$(P)TrigSrc-Sel") {
field( FTVL, "0x02020001")
field( FFVL, "0x02020002")
info( autosaveFields_pass0, "VAL")
alias("$(P)TrigSrc:0-Sel")
alias("$(P)TrigSrc$(s=:)0-Sel")
}

record(mbbo, "$(P)TrigSrc:1-Sel") {
record(mbbo, "$(P)TrigSrc$(s=:)1-Sel") {
field( DTYP, "Raw Soft Channel")
field( OUT , "$(P)TrigSrc-Sel_ PP")
field( UDF, "0")
Expand Down Expand Up @@ -78,7 +78,7 @@ record(mbbo, "$(P)TrigSrc:1-Sel") {
}

# placeholder to OPIs
record(mbbo, "$(P)TrigSrc:2-Sel") {
record(mbbo, "$(P)TrigSrc$(s=:)2-Sel") {
field(DISP, "1")
}

Expand Down Expand Up @@ -135,11 +135,11 @@ record(stringin, "$(P)TrigSrc-RB") {
#(only if TsInpMode = EGU).
#
record(ai, "$(P)EvtClkFreq-RB_") {
field( INP, "$(SYS){$(D)-EvtClk}Frequency-RB CP")
field( FLNK, "$(P)EvtClkFreq:Cont-RB_")
field( INP, "$(PP=$(SYS){$(D)-)EvtClk$(s=})Frequency-RB CP")
field( FLNK, "$(P)EvtClkFreq$(s=:)Cont-RB_")
}

record(ao, "$(P)EvtClkFreq:Cont-RB_") {
record(ao, "$(P)EvtClkFreq$(s=:)Cont-RB_") {
field( OUT, "$(P)Timestamp-RB.PROC")
field( VAL, "1")
}
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