add fpu over cv-x-if in tb (#392)

esl-epfl · Oct 5, 2023 · 1e77ff2 · 1e77ff2
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diff --git a/README.md b/README.md
@@ -182,8 +182,13 @@ First, you have to generate the SystemVerilog package and C header file of the c
 make mcu-gen
 ```
 
-To change the default cpu type (i.e., cv32e20), the default bus type (i.e., onetoM),
-the default continuous memory size (i.e., 2 continuous banks) or the default interleaved memory size (i.e., 0 interleaved banks):
+By default, `X-HEEP` deploys the [cv32e20](https://github.com/openhwgroup/cve2) RISC-V CPU.
+Other supported CPUs are: the [cv32e40p](https://github.com/openhwgroup/cv32e40p), [cv32e40x](https://github.com/openhwgroup/cv32e40x), and the [cv32e40px](https://github.com/esl-epfl/cv32e40px).
+The default bus type of `X-HEEP` is a single-master-at-a-time architecture, (called `onetoM`), but the cross-bar architecture is also supported by setting
+the bus to `NtoM`. Also, the user can select the number of 32kB banks addressed in continuous mode and/or the interleaved mode.
+By default, `X-HEEP` is generated with 2 continuous banks and 0 interleaved banks.
+
+Below an example that changes the default configuration:
 
 ```
 make mcu-gen CPU=cv32e40p BUS=NtoM MEMORY_BANKS=12 MEMORY_BANKS_IL=4

diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core
@@ -73,6 +73,7 @@ filesets:
   tb-utils:
     depend:
     - x-heep::tb-utils
+    - x-heep::tb-fpu-utils
 
   files_verilator_waiver:
     depend:
@@ -230,6 +231,12 @@ parameters:
     description: |
       Enables testbench JTAG DIPs. Admitted values: 1|0.
     default: 0
+  X_EXT:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
+    default: 0
   USE_EXTERNAL_DEVICE_EXAMPLE:
     datatype: int
     paramtype: vlogparam
@@ -324,6 +331,7 @@ targets:
     - COREV_PULP
     - FPU
     - JTAG_DPI
+    - X_EXT
     - USE_EXTERNAL_DEVICE_EXAMPLE
     - USE_UPF
     - REMOVE_OBI_FIFO
@@ -382,6 +390,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     tools:
@@ -401,6 +410,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     tools:
@@ -420,6 +430,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     tools:
@@ -435,6 +446,7 @@ targets:
     parameters:
     - PRIM_DEFAULT_IMPL=prim_pkg::your_target_technology
     - COREV_PULP
+    - X_EXT
     - FPU
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
@@ -457,6 +469,7 @@ targets:
     parameters:
       - COREV_PULP
       - FPU
+      - X_EXT
       - SYNTHESIS=true
       - VERILATOR=true
       - REMOVE_OBI_FIFO

diff --git a/docs/source/How_to/eXtendingHEEP.md b/docs/source/How_to/eXtendingHEEP.md
@@ -12,6 +12,18 @@ Here you can find a list of `X-HEEP` based open-source examples. If you want to
 * [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40x.
 
 
+In addition, the `X-HEEP` testbench has been extended with a `DMA`, dummy `PERIPHERALs` (including the `FLASH`), and a CORE-V-XIF compatible co-processor
+implementing the `RV32F` RISC-V ISA. This has been done to help us maintaining and verifying the extension interface.
+
+If you want to try the co-processor with a CORE-V-XIF compatible CPU as the `cv32e40px`, do as follow:
+
+```
+make mcu-gen CPU=cv32e40px
+make verilator-sim FUSESOC_PARAM="--X_EXT=1"
+make app PROJECT=example_matfadd ARCH=rv32imfc
+./Vtestharness +firmware=../../../sw/build/main.hex
+```
+
 ## Vendorizing X-HEEP
 
 In order to vendorize `X-HEEP` create inside your repository's base directory (`BASE`) a `hw/vendor` directory containing a file named `esl_epfl_x_heep.vendor.hjson`:

diff --git a/hw/core-v-mini-mcu/cpu_subsystem.sv b/hw/core-v-mini-mcu/cpu_subsystem.sv
@@ -175,7 +175,7 @@ module cpu_subsystem
     // instantiate the core
     cv32e40x_core #(
         .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS),
-        .X_EXT(X_EXT),
+        .X_EXT(X_EXT[0]),
         .DBG_NUM_TRIGGERS('0)
     ) cv32e40x_core_i (
         // Clock and reset
@@ -307,30 +307,35 @@ module cpu_subsystem
 
         // CORE-V-XIF
         // Compressed interface
-        .x_compressed_valid_o(),
-        .x_compressed_ready_i(),
-        .x_compressed_req_o(),
-        .x_compressed_resp_i('0),
+        .x_compressed_valid_o(xif_compressed_if.compressed_valid),
+        .x_compressed_ready_i(xif_compressed_if.compressed_ready),
+        .x_compressed_req_o  (xif_compressed_if.compressed_req),
+        .x_compressed_resp_i (xif_compressed_if.compressed_resp),
+
         // Issue Interface
-        .x_issue_valid_o(),
-        .x_issue_ready_i(),
-        .x_issue_req_o(),
-        .x_issue_resp_i('0),
+        .x_issue_valid_o(xif_issue_if.issue_valid),
+        .x_issue_ready_i(xif_issue_if.issue_ready),
+        .x_issue_req_o  (xif_issue_if.issue_req),
+        .x_issue_resp_i (xif_issue_if.issue_resp),
+
         // Commit Interface
-        .x_commit_valid_o(),
-        .x_commit_o(),
-        // Memory request/response Interface
-        .x_mem_valid_i(),
-        .x_mem_ready_o(),
-        .x_mem_req_i('0),
-        .x_mem_resp_o(),
+        .x_commit_valid_o(xif_commit_if.commit_valid),
+        .x_commit_o(xif_commit_if.commit),
+
+        // Memory Request/Response Interface
+        .x_mem_valid_i(xif_mem_if.mem_valid),
+        .x_mem_ready_o(xif_mem_if.mem_ready),
+        .x_mem_req_i  (xif_mem_if.mem_req),
+        .x_mem_resp_o (xif_mem_if.mem_resp),
+
         // Memory Result Interface
-        .x_mem_result_valid_o(),
-        .x_mem_result_o(),
+        .x_mem_result_valid_o(xif_mem_result_if.mem_result_valid),
+        .x_mem_result_o(xif_mem_result_if.mem_result),
+
         // Result Interface
-        .x_result_valid_i(),
-        .x_result_ready_o(),
-        .x_result_i('0),
+        .x_result_valid_i(xif_result_if.result_valid),
+        .x_result_ready_o(xif_result_if.result_ready),
+        .x_result_i(xif_result_if.result),
 
         .irq_i    (irq_i),
         .irq_ack_o(irq_ack_o),

diff --git a/hw/ip_examples/fpu_ss_wrapper/fpu_ss_wrapper.sv b/hw/ip_examples/fpu_ss_wrapper/fpu_ss_wrapper.sv
@@ -0,0 +1,84 @@
+// Copyright 2023 David Mallasén Quintana
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you 
+// may not use this file except in compliance with the License, or, at your
+// option, the Apache License version 2.0. You may obtain a copy of the 
+// License at https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work 
+// distributed under the License is distributed on an “AS IS” BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 
+// License for the specific language governing permissions and limitations 
+// under the License.
+//
+// Author: David Mallasén <dmallase@ucm.es>
+// Description: Wrapper for the fpu_ss, adapting the XIF signals
+
+module fpu_ss_wrapper #(
+    parameter                                 PULP_ZFINX         = 0,
+    parameter                                 INPUT_BUFFER_DEPTH = 1,
+    parameter                                 OUT_OF_ORDER       = 0,
+    parameter                                 FORWARDING         = 1,
+    parameter fpnew_pkg::fpu_features_t       FPU_FEATURES       = fpu_ss_pkg::FPU_FEATURES,
+    parameter fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = fpu_ss_pkg::FPU_IMPLEMENTATION
+) (
+    // Clock and Reset
+    input logic clk_i,
+    input logic rst_ni,
+
+    // eXtension interface
+    if_xif.coproc_compressed xif_compressed_if,
+    if_xif.coproc_issue      xif_issue_if,
+    if_xif.coproc_commit     xif_commit_if,
+    if_xif.coproc_mem        xif_mem_if,
+    if_xif.coproc_mem_result xif_mem_result_if,
+    if_xif.coproc_result     xif_result_if
+);
+
+  fpu_ss #(
+      .PulpDivsqrt(1'b0),
+      .PULP_ZFINX(PULP_ZFINX),
+      .INPUT_BUFFER_DEPTH(INPUT_BUFFER_DEPTH),
+      .OUT_OF_ORDER(OUT_OF_ORDER),
+      .FORWARDING(FORWARDING),
+      .FPU_FEATURES(FPU_FEATURES),
+      .FPU_IMPLEMENTATION(FPU_IMPLEMENTATION)
+  ) fpu_ss_i (
+      // Clock and reset
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // Compressed Interface
+      .x_compressed_valid_i(xif_compressed_if.compressed_valid),
+      .x_compressed_ready_o(xif_compressed_if.compressed_ready),
+      .x_compressed_req_i  (xif_compressed_if.compressed_req),
+      .x_compressed_resp_o (xif_compressed_if.compressed_resp),
+
+      // Issue Interface
+      .x_issue_valid_i(xif_issue_if.issue_valid),
+      .x_issue_ready_o(xif_issue_if.issue_ready),
+      .x_issue_req_i  (xif_issue_if.issue_req),
+      .x_issue_resp_o (xif_issue_if.issue_resp),
+
+      // Commit Interface
+      .x_commit_valid_i(xif_commit_if.commit_valid),
+      .x_commit_i(xif_commit_if.commit),
+
+      // Memory Request/Response Interface
+      .x_mem_valid_o(xif_mem_if.mem_valid),
+      .x_mem_ready_i(xif_mem_if.mem_ready),
+      .x_mem_req_o  (xif_mem_if.mem_req),
+      .x_mem_resp_i (xif_mem_if.mem_resp),
+
+      // Memory Result Interface
+      .x_mem_result_valid_i(xif_mem_result_if.mem_result_valid),
+      .x_mem_result_i(xif_mem_result_if.mem_result),
+
+      // Result Interface
+      .x_result_valid_o(xif_result_if.result_valid),
+      .x_result_ready_i(xif_result_if.result_ready),
+      .x_result_o(xif_result_if.result)
+  );
+
+endmodule
diff --git a/hw/vendor/esl_epfl_cv32e40px.core b/hw/vendor/esl_epfl_cv32e40px.core
@@ -38,12 +38,12 @@ filesets:
     - esl_epfl_cv32e40px/rtl/cv32e40px_sleep_unit.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_apu_disp.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_x_disp
     - esl_epfl_cv32e40px/rtl/cv32e40px_fifo.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
     - esl_epfl_cv32e40px/rtl/cv32e40px_top.sv
     file_type: systemVerilogSource
 
-
   files_clk_gate:
     files:
     - esl_epfl_cv32e40px/bhv/cv32e40px_sim_clock_gate.sv

diff --git a/hw/vendor/esl_epfl_cv32e40px.lock.hjson b/hw/vendor/esl_epfl_cv32e40px.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/cv32e40px.git
-    rev: 326891e200365b2558511e6deb8e444eb8daf977
+    rev: acf3442b414725191fb7a2027facd0b5b4123c1c
   }
 }
diff --git a/hw/vendor/esl_epfl_cv32e40px.vendor.hjson b/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/cv32e40px.git",
-    rev: "326891e200365b2558511e6deb8e444eb8daf977",
+    rev: "acf3442b414725191fb7a2027facd0b5b4123c1c",
   },
 
   patch_dir: "patches/esl_epfl_cv32e40px",

diff --git a/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv b/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
@@ -463,6 +463,7 @@ module cv32e40px_core
   //                                              //
   //////////////////////////////////////////////////
   cv32e40px_if_stage #(
+      .COREV_X_IF (COREV_X_IF),
       .COREV_PULP (COREV_PULP),
       .PULP_OBI   (PULP_OBI),
       .PULP_SECURE(PULP_SECURE),

diff --git a/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv b/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
@@ -1015,7 +1015,7 @@ module cv32e40px_id_stage
   logic [1:0] x_mem_data_type_id;
 
   generate
-    if (COREV_X_IF) begin : gen_x_disp
+    if (COREV_X_IF != 0) begin : gen_x_disp
       ////////////////////////////////////////
       //  __  __     ____ ___ ____  ____    //
       //  \ \/ /    |  _ \_ _/ ___||  _ \   //
@@ -1138,13 +1138,13 @@ module cv32e40px_id_stage
       always_comb begin
         x_mem_data_type_id = 2'b00;
         case (x_mem_req_i.size)
-          2'b00: x_mem_data_type_id = 2'b10;  // SB
-          2'b01: x_mem_data_type_id = 2'b01;  // SH
-          2'b10: x_mem_data_type_id = 2'b00;  // SW
+          3'd0: x_mem_data_type_id = 2'b10;  // SB
+          3'd1: x_mem_data_type_id = 2'b01;  // SH
+          3'd2: x_mem_data_type_id = 2'b00;  // SW
+          default: x_mem_data_type_id = 2'b00;  // SW
         endcase
       end
 
-
     end else begin : gen_no_x_disp
 
       // default illegal instruction assignment

diff --git a/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_if_stage.sv b/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_if_stage.sv
@@ -291,9 +291,9 @@ module cv32e40px_if_stage #(
 
 
   generate
-    if (COREV_X_IF) begin
+    if (COREV_X_IF != 0) begin
       assign x_compressed_valid_o = illegal_c_insn_dec;
-      assign x_compressed_req_o.instr = instr_aligned;
+      assign x_compressed_req_o.instr = instr_aligned[15:0];
       assign x_compressed_req_o.mode = 2'b00;  // Machine Mode
       assign x_compressed_req_o.id = x_compressed_id_i;
 

diff --git a/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv b/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
@@ -98,7 +98,7 @@ module cv32e40px_x_disp
   // scoreboard, id and satus signals
   logic [31:0] scoreboard_q, scoreboard_d;
   logic [3:0] id_q, id_d;
-  logic [3:0] instr_offloaded_q, instr_offloaded_d;
+  logic instr_offloaded_q, instr_offloaded_d;
   logic [3:0] mem_counter_q, mem_counter_d;
   logic dep;
   logic outstanding_mem;
@@ -182,7 +182,7 @@ module cv32e40px_x_disp
   always_comb begin
     scoreboard_d = scoreboard_q;
     if (x_issue_resp_writeback_i & x_issue_valid_o & x_issue_ready_i
-        & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & x_result_rd_i)) begin
+        & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & (x_result_rd_i != '0))) begin
       scoreboard_d[waddr_id_i] = 1'b1;
     end
     if (x_result_valid_i & x_result_we_i) begin