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add napot bus
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davideschiavone committed Sep 14, 2023
1 parent 8e9d91a commit 29ef98c
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Showing 6 changed files with 11 additions and 9 deletions.
3 changes: 2 additions & 1 deletion hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -217,7 +217,8 @@ module ao_peripheral_subsystem
.NoIndices(core_v_mini_mcu_pkg::AO_PERIPHERALS),
.NoRules(core_v_mini_mcu_pkg::AO_PERIPHERALS),
.addr_t(logic [31:0]),
.rule_t(addr_map_rule_pkg::addr_map_rule_t)
.rule_t(addr_map_rule_pkg::addr_map_rule_t),
.Napot(1)
) i_addr_decode_soc_regbus_periph_xbar (
.addr_i(peripheral_req.addr),
.addr_map_i(core_v_mini_mcu_pkg::AO_PERIPHERALS_ADDR_RULES),
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3 changes: 2 additions & 1 deletion hw/core-v-mini-mcu/peripheral_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -238,7 +238,8 @@ module peripheral_subsystem
.NoIndices(core_v_mini_mcu_pkg::PERIPHERALS),
.NoRules(core_v_mini_mcu_pkg::PERIPHERALS),
.addr_t(logic [31:0]),
.rule_t(addr_map_rule_pkg::addr_map_rule_t)
.rule_t(addr_map_rule_pkg::addr_map_rule_t),
.Napot(1)
) i_addr_decode_soc_regbus_periph_xbar (
.addr_i(peripheral_req.addr),
.addr_map_i(core_v_mini_mcu_pkg::PERIPHERALS_ADDR_RULES),
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3 changes: 2 additions & 1 deletion hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -238,7 +238,8 @@ module peripheral_subsystem
.NoIndices(core_v_mini_mcu_pkg::PERIPHERALS),
.NoRules(core_v_mini_mcu_pkg::PERIPHERALS),
.addr_t(logic [31:0]),
.rule_t(addr_map_rule_pkg::addr_map_rule_t)
.rule_t(addr_map_rule_pkg::addr_map_rule_t),
.Napot(1)
) i_addr_decode_soc_regbus_periph_xbar (
.addr_i(peripheral_req.addr),
.addr_map_i(core_v_mini_mcu_pkg::PERIPHERALS_ADDR_RULES),
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6 changes: 2 additions & 4 deletions hw/core-v-mini-mcu/system_bus.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -206,9 +206,10 @@ module system_bus
error_slave_resp_rvalid <= 1'b0;
end else begin
`ifndef SYNTHESIS
if(rst_ni)
$display("%t Out of bound memory access 0x%08x", $time, error_slave_req.addr);
`endif
error_slave_resp_rvalid <= error_slave_resp.gnt;
error_slave_resp_rvalid <= error_slave_resp.gnt;
end
end

Expand All @@ -220,9 +221,6 @@ module system_bus
end
`endif




// 1-to-2 demux crossbars
// ------------------------
// These crossbars forward each master to a port on the internal crossbar or
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3 changes: 2 additions & 1 deletion hw/core-v-mini-mcu/system_xbar.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,8 @@ module system_xbar
.NoIndices(XBAR_NSLAVE),
.NoRules(XBAR_NSLAVE),
.addr_t(logic [31:0]),
.rule_t(addr_map_rule_pkg::addr_map_rule_t)
.rule_t(addr_map_rule_pkg::addr_map_rule_t),
.Napot(1)
) addr_decode_i (
.addr_i(master_req_i[i].addr),
.addr_map_i,
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2 changes: 1 addition & 1 deletion hw/core-v-mini-mcu/xbar_varlat_one_to_n.sv
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ module xbar_varlat_one_to_n #(
.NoRules (NUM_RULES),
.addr_t (logic [31:0]),
.rule_t (addr_map_rule_pkg::addr_map_rule_t),
.Napot (1'b0)
.Napot (1'b1)
) u_addr_decode (
.addr_i (master_req_i.addr),
.addr_map_i (addr_map_i),
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