add Coremark and update cv32e40p (#465)

--------- Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr> Co-authored-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
esl-epfl · Mar 4, 2024 · 88c8919 · 88c8919
1 parent 170c9b4
commit 88c8919
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diff --git a/README.md b/README.md
@@ -251,7 +251,7 @@ make app TARGET=pynq-z2
 Or, if you use the OpenHW Group [GCC](https://www.embecosm.com/resources/tool-chain-downloads/#corev) compiler with CORE_PULP extensions, make sure to point the `RISCV` env variable to the OpenHW Group compiler, then just run:
 
 ```
-make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp1p0_xcvmem1p0_xcvmac1p0_xcvbi1p0_xcvalu1p0_xcvsimd1p0_xcvbitmanip1p0
+make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp_xcvmem_xcvmac_xcvbi_xcvalu_xcvsimd_xcvbitmanip
 ```
 
 This will create the executable file to be loaded into your target system (ASIC, FPGA, Simulation).

diff --git a/hw/vendor/openhwgroup_cv32e40p.lock.hjson b/hw/vendor/openhwgroup_cv32e40p.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/openhwgroup/cv32e40p.git
-    rev: c8d65849ec060c6f7bc62325b46ba0ab7eae8805
+    rev: 370cf19b3b60cbdc847ff102551392dd501029a2
   }
 }
diff --git a/hw/vendor/openhwgroup_cv32e40p.vendor.hjson b/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/openhwgroup/cv32e40p.git",
-    rev: "c8d65849ec060c6f7bc62325b46ba0ab7eae8805",
+    rev: "370cf19b3b60cbdc847ff102551392dd501029a2",
   },
 
   patch_dir: "patches/openhwgroup_cv32e40p",

diff --git a/hw/vendor/openhwgroup_cv32e40p/.gitignore b/hw/vendor/openhwgroup_cv32e40p/.gitignore
@@ -18,3 +18,9 @@ TAGS
 /build
 /Bender.lock
 /Bender.local
+golden_reference_design
+golden.src
+revised.src
+cadence_conformal
+synopsys_formality
+questa_autocheck
diff --git a/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh b/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
@@ -679,22 +679,22 @@ class instr_trace_t;
       // decode and print instruction
       case (instr[11:8])
         // cv.starti, cv.endi
-        4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, rd[0], imm_iz_type);
+        4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, instr[7], imm_iz_type);
         // cv.counti
-        4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, rd[0], imm_iz_type);
+        4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, instr[7], imm_iz_type);
         // cv.start, cv.end, cv.count
         4'b0001, 4'b0011, 4'b0101: begin
           regs_read.push_back('{rs1, rs1_value, 0});
-          str = $sformatf("%-16s %d, %s", mnemonic, rd[0], regAddrToStr(rs1));
+          str = $sformatf("%-16s %d, %s", mnemonic, instr[7], regAddrToStr(rs1));
         end
         // cv.setupi
         4'b0110: begin
-          str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, rd[0], imm_iz_type, rs1);
+          str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, instr[7], imm_iz_type, rs1);
         end
         // cv.setup
         4'b0111: begin
           regs_read.push_back('{rs1, rs1_value, 0});
-          str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, rd[0], regAddrToStr(rs1), imm_iz_type);
+          str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, instr[7], regAddrToStr(rs1), imm_iz_type);
         end
       endcase
     end
@@ -861,7 +861,7 @@ class instr_trace_t;
           endcase
           str_sci  = "";
         end
-  
+
         // shuffle/pack
         6'b110000: begin
           if (instr[14:12] == 3'b111) begin