fix space

esl-epfl · Sep 12, 2024 · a6e8893 · a6e8893
1 parent b5e76cf
commit a6e8893
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/hw/fpga/prim_xilinx_clk.sv b/hw/fpga/prim_xilinx_clk.sv
@@ -14,8 +14,8 @@ module xilinx_clk_gating (
   // In the Zynq UltraScale+, it can be implemented as BUFGCE without trouble, since there
   // are > 500 BUFGCEs and the rules for cascading are more relaxed.
   // NOTE: This **cannot** be substituted by a latch+and
- assign clk_o = clk_i;
- 
+  assign clk_o = clk_i;
+
 endmodule
 
 module xilinx_clk_inverter (