add minimal configuration for mcu-gen (#378)

README.md

@@ -192,6 +192,16 @@ make mcu-gen CPU=cv32e40p BUS=NtoM MEMORY_BANKS=12 MEMORY_BANKS_IL=4
 The last command generates x-heep with the cv32e40p core, with a parallel bus, and 16 memory banks (12 continuous and 4 interleaved),
 each 32KB, for a total memory of 512KB.
 
+If you are using `X-HEEP` just as a controller for your own system and you do not need any peripheral, you can use the `minimal` configuration file
+when generating the MCU as:
+
+```
+make mcu-gen MCU_CFG=mcu_cfg_minimal.hjson
+```
+
+The `minimal` configuration is a work-in-progress, thus not all the APPs have been tested.
+
+
 ## Compiling Software
 
 Don't forget to set the `RISCV` env variable to the compiler folder (without the `/bin` included).

hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl

@@ -295,7 +295,11 @@ module peripheral_subsystem
   );
 % else:
   assign msip_o = '0;
-  assign irq_id = '0;
+
+  for(genvar i=0; i<rv_plic_reg_pkg::NumTarget; i=i+1) begin
+    assign irq_id[i] = '0;
+  end
+
   assign irq_plic_o = '0;
   assign plic_tl_d2h = '0;
 % endif
@@ -536,8 +540,8 @@ module peripheral_subsystem
   assign i2s_ws_o         = 1'b0;
   assign i2s_sd_oe_o      = 1'b0;
   assign i2s_sd_o         = 1'b0;
-  assign intr_i2s_event   = 1'b0;
-  assing i2s_rx_valid_o   = 1'b0;
+  assign i2s_intr_event   = 1'b0;
+  assign i2s_rx_valid_o   = 1'b0;
 % endif
 % endif
 % endfor

mcu_cfg_minimal.hjson

@@ -0,0 +1,214 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Derived from Occamy: https://github.com/pulp-platform/snitch/blob/master/hw/system/occamy/src/occamy_cfg.hjson
+// Peripherals configuration for core-v-mini-mcu.
+{
+
+    cpu_type: cv32e20
+
+    bus_type: onetoM
+
+    ram: {
+        address: 0x00000000, #only tried with 0, cannot be changed for now
+        numbanks: 2, #each bank is 32kB, cannot be changed for now
+        numbanks_interleaved: 0,
+    },
+
+    linker_script: {
+        #value used for the on-chip linker script, the on-flash linker script is generated using FLASH values and the whole RAM values
+        onchip_ls: {
+            code: {
+                address: 0x00000000,
+                lenght: 0x00000C800, #minimum size for freeRTOS and clang
+            }
+            data: {
+                address: 0x00000C800,
+                lenght: whatisleft, #keyword used to calculate the size as: ram.length - code.lenght
+            }
+        },
+    }
+
+    debug: {
+        address: 0x10000000,
+        length:  0x00100000,
+    },
+
+    ao_peripherals: {
+        address: 0x20000000,
+        length:  0x00100000,
+        soc_ctrl: {
+            offset:  0x00000000,
+            length:  0x00010000,
+            path:    "./hw/ip/soc_ctrl/data/soc_ctrl.hjson"
+        },
+        bootrom: {
+            offset:  0x00010000,
+            length:  0x00010000,
+        },
+        spi_flash: {
+            offset:  0x00020000,
+            length:  0x00008000,
+        },
+        spi_memio: {
+            offset:  0x00028000,
+            length:  0x00008000,
+        },
+        spi_host: {
+            offset:  0x00030000,
+            length:  0x00010000,
+            path:    "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson"
+        },
+        power_manager: {
+            offset:  0x00040000,
+            length:  0x00010000,
+            path:    "./hw/ip/power_manager/data/power_manager.hjson"
+        },
+        rv_timer_ao: {
+            offset:  0x00050000,
+            length:  0x00010000,
+        },
+        dma: {
+            offset:  0x00060000,
+            length:  0x00010000,
+            path:    "./hw/ip/dma/data/dma.hjson"
+        },
+        fast_intr_ctrl: {
+            offset:  0x00070000,
+            length:  0x00010000,
+            path:    "./hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson"
+        },
+        ext_peripheral: {
+            offset:  0x00080000,
+            length:  0x00010000,
+        },
+        pad_control: {
+            offset:  0x00090000,
+            length:  0x00010000,
+        },
+        gpio_ao: {
+            offset:  0x000A0000,
+            length:  0x00010000,
+        },
+        uart: {
+            offset:  0x000B0000,
+            length:  0x00010000,
+            path:    "./hw/vendor/lowrisc_opentitan/hw/ip/uart/data/uart.hjson"
+        },
+    },
+
+    peripherals: {
+        address: 0x30000000,
+        length:  0x00100000,
+        rv_plic: {
+            offset:  0x00000000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_plic/data/rv_plic.hjson"
+        },
+        gpio: {
+            offset:  0x00020000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/vendor/pulp_platform_gpio/gpio_regs.hjson"
+        },
+        i2c: {
+            offset:  0x00030000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/vendor/lowrisc_opentitan/hw/ip/i2c/data/i2c.hjson"
+        },
+        rv_timer: {
+            offset:  0x00040000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_timer/data/rv_timer.hjson"
+        },
+        spi2: {
+            offset:  0x00050000,
+            length:  0x00010000,
+            is_included: "no",
+        },
+        pdm2pcm: {
+            offset:  0x00060000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/ip/pdm2pcm/data/pdm2pcm.hjson"
+        },
+        i2s: {
+            offset:  0x00070000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/ip/i2s/data/i2s.hjson"
+        },
+    },
+
+    flash_mem: {
+        address: 0x40000000,
+        length:  0x01000000,
+    },
+
+    ext_slaves: {
+        address: 0xF0000000,
+        length:  0x01000000,
+    },
+
+    interrupts: {
+        number: 64, // Do not change this number!
+        list: {
+            // First one is always zero
+            null_intr:               0,
+            uart_intr_tx_watermark:  1,
+            uart_intr_rx_watermark:  2,
+            uart_intr_tx_empty:      3,
+            uart_intr_rx_overflow:   4,
+            uart_intr_rx_frame_err:  5,
+            uart_intr_rx_break_err:  6,
+            uart_intr_rx_timeout:    7,
+            uart_intr_rx_parity_err: 8,
+            gpio_intr_8:             9,
+            gpio_intr_9:             10,
+            gpio_intr_10:            11,
+            gpio_intr_11:            12,
+            gpio_intr_12:            13,
+            gpio_intr_13:            14,
+            gpio_intr_14:            15,
+            gpio_intr_15:            16,
+            gpio_intr_16:            17,
+            gpio_intr_17:            18,
+            gpio_intr_18:            19,
+            gpio_intr_19:            20,
+            gpio_intr_20:            21,
+            gpio_intr_21:            22,
+            gpio_intr_22:            23,
+            gpio_intr_23:            24,
+            gpio_intr_24:            25,
+            gpio_intr_25:            26,
+            gpio_intr_26:            27,
+            gpio_intr_27:            28,
+            gpio_intr_28:            29,
+            gpio_intr_29:            30,
+            gpio_intr_30:            31,
+            gpio_intr_31:            32,
+            intr_fmt_watermark:      33,
+            intr_rx_watermark:       34,
+            intr_fmt_overflow:       35,
+            intr_rx_overflow:        36,
+            intr_nak:                37,
+            intr_scl_interference:   38,
+            intr_sda_interference:   39,
+            intr_stretch_timeout:    40,
+            intr_sda_unstable:       41,
+            intr_trans_complete:     42,
+            intr_tx_empty:           43,
+            intr_tx_nonempty:        44,
+            intr_tx_overflow:        45,
+            intr_acq_overflow:       46,
+            intr_ack_stop:           47,
+            intr_host_timeout:       48,
+            spi2_intr_event:         49,
+            i2s_intr_event:          50,
+            dma_window_intr:         51,
+        }
+    }
+}