Clean up unnecessary unsafe blocks

esp-rs · Jul 20, 2023 · 311ff3d · 311ff3d
1 parent 41361a5
commit 311ff3d
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Showing 4 changed files with 153 additions and 160 deletions.
diff --git a/esp-hal-common/src/clock/clocks_ll/esp32c2.rs b/esp-hal-common/src/clock/clocks_ll/esp32c2.rs
@@ -42,18 +42,18 @@ const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 3;
 pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllClock) {
     let system = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
-    unsafe {
-        let div_ref: u32;
-        let div7_0: u32;
-        let dr1: u32;
-        let dr3: u32;
-        let dchgp: u32;
-        let dcur: u32;
-        let dbias: u32;
-        let i2c_bbpll_lref: u32;
-        let i2c_bbpll_div_7_0: u32;
-        let i2c_bbpll_dcur: u32;
+    let div_ref: u32;
+    let div7_0: u32;
+    let dr1: u32;
+    let dr3: u32;
+    let dchgp: u32;
+    let dcur: u32;
+    let dbias: u32;
+    let i2c_bbpll_lref: u32;
+    let i2c_bbpll_div_7_0: u32;
+    let i2c_bbpll_dcur: u32;
 
+    unsafe {
         let clear_reg_mask = |reg, mask: u32| {
             (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !mask)
         };
@@ -63,53 +63,52 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl
 
         clear_reg_mask(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
         set_reg_mask(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    }
 
-        // Set this register to let the digital part know 480M PLL is used
-        system
-            .cpu_per_conf
-            .modify(|_, w| w.pll_freq_sel().set_bit());
-
-        // Configure 480M PLL
-        match xtal_freq {
-            XtalClock::RtcXtalFreq26M => {
-                div_ref = 12;
-                div7_0 = 236;
-                dr1 = 4;
-                dr3 = 4;
-                dchgp = 0;
-                dcur = 0;
-                dbias = 2;
-            }
-            XtalClock::RtcXtalFreq40M | XtalClock::RtcXtalFreqOther(_) => {
-                div_ref = 0;
-                div7_0 = 8;
-                dr1 = 0;
-                dr3 = 0;
-                dchgp = 5;
-                dcur = 3;
-                dbias = 2;
-            }
+    // Set this register to let the digital part know 480M PLL is used
+    system
+        .cpu_per_conf
+        .modify(|_, w| w.pll_freq_sel().set_bit());
+
+    // Configure 480M PLL
+    match xtal_freq {
+        XtalClock::RtcXtalFreq26M => {
+            div_ref = 12;
+            div7_0 = 236;
+            dr1 = 4;
+            dr3 = 4;
+            dchgp = 0;
+            dcur = 0;
+            dbias = 2;
         }
+        XtalClock::RtcXtalFreq40M | XtalClock::RtcXtalFreqOther(_) => {
+            div_ref = 0;
+            div7_0 = 8;
+            dr1 = 0;
+            dr3 = 0;
+            dchgp = 5;
+            dcur = 3;
+            dbias = 2;
+        }
+    }
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
 
-        i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
-        i2c_bbpll_div_7_0 = div7_0;
-        i2c_bbpll_dcur =
-            (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
+    i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
+    i2c_bbpll_div_7_0 = div7_0;
+    i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
-    }
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
 }
 
 pub(crate) fn esp32c2_rtc_bbpll_enable() {

diff --git a/esp-hal-common/src/clock/clocks_ll/esp32c3.rs b/esp-hal-common/src/clock/clocks_ll/esp32c3.rs
@@ -46,18 +46,17 @@ const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 2;
 pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) {
     let system = unsafe { &*crate::peripherals::SYSTEM::ptr() };
 
+    let div_ref: u32;
+    let div7_0: u32;
+    let dr1: u32;
+    let dr3: u32;
+    let dchgp: u32;
+    let dcur: u32;
+    let dbias: u32;
+    let i2c_bbpll_lref: u32;
+    let i2c_bbpll_div_7_0: u32;
+    let i2c_bbpll_dcur: u32;
     unsafe {
-        let div_ref: u32;
-        let div7_0: u32;
-        let dr1: u32;
-        let dr3: u32;
-        let dchgp: u32;
-        let dcur: u32;
-        let dbias: u32;
-        let i2c_bbpll_lref: u32;
-        let i2c_bbpll_div_7_0: u32;
-        let i2c_bbpll_dcur: u32;
-
         let clear_reg_mask = |reg, mask: u32| {
             (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !mask)
         };
@@ -67,110 +66,109 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo
 
         clear_reg_mask(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
         set_reg_mask(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    }
 
-        if matches!(pll_freq, PllClock::Pll480MHz) {
-            // Set this register to let the digital part know 480M PLL is used
-            system
-                .cpu_per_conf
-                .modify(|_, w| w.pll_freq_sel().set_bit());
-
-            // Configure 480M PLL
-            match xtal_freq {
-                XtalClock::RtcXtalFreq40M => {
-                    div_ref = 0;
-                    div7_0 = 8;
-                    dr1 = 0;
-                    dr3 = 0;
-                    dchgp = 5;
-                    dcur = 3;
-                    dbias = 2;
-                }
-
-                XtalClock::RtcXtalFreq32M => {
-                    div_ref = 1;
-                    div7_0 = 26;
-                    dr1 = 1;
-                    dr3 = 1;
-                    dchgp = 4;
-                    dcur = 0;
-                    dbias = 2;
-                }
-
-                XtalClock::RtcXtalFreqOther(_) => {
-                    div_ref = 0;
-                    div7_0 = 8;
-                    dr1 = 0;
-                    dr3 = 0;
-                    dchgp = 5;
-                    dcur = 3;
-                    dbias = 2;
-                }
+    if matches!(pll_freq, PllClock::Pll480MHz) {
+        // Set this register to let the digital part know 480M PLL is used
+        system
+            .cpu_per_conf
+            .modify(|_, w| w.pll_freq_sel().set_bit());
+
+        // Configure 480M PLL
+        match xtal_freq {
+            XtalClock::RtcXtalFreq40M => {
+                div_ref = 0;
+                div7_0 = 8;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 3;
+                dbias = 2;
             }
 
-            regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
-        } else {
-            // Clear this register to let the digital part know 320M PLL is used
-            system
-                .cpu_per_conf
-                .modify(|_, w| w.pll_freq_sel().clear_bit());
-
-            // Configure 320M PLL
-            match xtal_freq {
-                XtalClock::RtcXtalFreq40M => {
-                    div_ref = 0;
-                    div7_0 = 4;
-                    dr1 = 0;
-                    dr3 = 0;
-                    dchgp = 5;
-                    dcur = 3;
-                    dbias = 2;
-                }
-
-                XtalClock::RtcXtalFreq32M => {
-                    div_ref = 1;
-                    div7_0 = 6;
-                    dr1 = 0;
-                    dr3 = 0;
-                    dchgp = 5;
-                    dcur = 3;
-                    dbias = 2;
-                }
-
-                XtalClock::RtcXtalFreqOther(_) => {
-                    div_ref = 0;
-                    div7_0 = 4;
-                    dr1 = 0;
-                    dr3 = 0;
-                    dchgp = 5;
-                    dcur = 3;
-                    dbias = 2;
-                }
+            XtalClock::RtcXtalFreq32M => {
+                div_ref = 1;
+                div7_0 = 26;
+                dr1 = 1;
+                dr3 = 1;
+                dchgp = 4;
+                dcur = 0;
+                dbias = 2;
             }
 
-            regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
+            XtalClock::RtcXtalFreqOther(_) => {
+                div_ref = 0;
+                div7_0 = 8;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 3;
+                dbias = 2;
+            }
         }
 
-        i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
-        i2c_bbpll_div_7_0 = div7_0;
-        i2c_bbpll_dcur =
-            (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
+        regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
+    } else {
+        // Clear this register to let the digital part know 320M PLL is used
+        system
+            .cpu_per_conf
+            .modify(|_, w| w.pll_freq_sel().clear_bit());
+
+        // Configure 320M PLL
+        match xtal_freq {
+            XtalClock::RtcXtalFreq40M => {
+                div_ref = 0;
+                div7_0 = 4;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 3;
+                dbias = 2;
+            }
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
+            XtalClock::RtcXtalFreq32M => {
+                div_ref = 1;
+                div7_0 = 6;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 3;
+                dbias = 2;
+            }
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+            XtalClock::RtcXtalFreqOther(_) => {
+                div_ref = 0;
+                div7_0 = 4;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 3;
+                dbias = 2;
+            }
+        }
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
+        regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
+    }
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+    i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
+    i2c_bbpll_div_7_0 = div7_0;
+    i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
 
-        regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
 
-        regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
-    }
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+
+    regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
+
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
+
+    regi2c_write_mask!(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
 }
 
 pub(crate) fn esp32c3_rtc_bbpll_enable() {

diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32c2.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32c2.rs
@@ -28,10 +28,8 @@ const I2C_ULP_IR_FORCE_XPD_CK_LSB: u32 = 2;
 pub(crate) fn init() {
     let rtc_cntl = unsafe { &*RTC_CNTL::ptr() };
 
-    unsafe {
-        regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
-        regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
-    }
+    regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
+    regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
 
     unsafe {
         rtc_cntl
@@ -52,9 +50,9 @@ pub(crate) fn init() {
     unsafe {
         rtc_cntl.int_ena_rtc.write(|w| w.bits(0));
         rtc_cntl.int_clr_rtc.write(|w| w.bits(u32::MAX));
-
-        regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
     }
+
+    regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
 }
 
 pub(crate) fn configure_clock() {

diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32c3.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32c3.rs
@@ -28,11 +28,9 @@ const I2C_ULP_IR_FORCE_XPD_CK_LSB: u32 = 2;
 pub(crate) fn init() {
     let rtc_cntl = unsafe { &*RTC_CNTL::ptr() };
 
-    unsafe {
-        regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
+    regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
 
-        regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
-    }
+    regi2c_write_mask!(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
 
     rtc_cntl.ana_conf.modify(|_, w| w.pvtmon_pu().clear_bit());
 
@@ -82,9 +80,9 @@ pub(crate) fn init() {
     unsafe {
         rtc_cntl.int_ena_rtc.write(|w| w.bits(0));
         rtc_cntl.int_clr_rtc.write(|w| w.bits(u32::MAX));
-
-        regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
     }
+
+    regi2c_write_mask!(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
 }
 
 pub(crate) fn configure_clock() {