PeripheralRef for SYSTEM/DPORT (#305)

esp-rs · Dec 14, 2022 · 39c5a04 · 39c5a04
1 parent 66c1944
commit 39c5a04
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Showing 6 changed files with 15 additions and 8 deletions.
diff --git a/esp-hal-common/src/peripherals/esp32.rs b/esp-hal-common/src/peripherals/esp32.rs
@@ -61,5 +61,6 @@ mod peripherals {
         UART0,
         UART1,
         UART2,
+        DPORT,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32c2.rs b/esp-hal-common/src/peripherals/esp32c2.rs
@@ -41,5 +41,6 @@ mod peripherals {
         SYSTIMER,
         UART0,
         UART1,
+        SYSTEM,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32c3.rs b/esp-hal-common/src/peripherals/esp32c3.rs
@@ -53,5 +53,6 @@ mod peripherals {
         UART0,
         UART1,
         USB_DEVICE,
+        SYSTEM,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32s2.rs b/esp-hal-common/src/peripherals/esp32s2.rs
@@ -60,5 +60,6 @@ mod peripherals {
         SYSTIMER,
         UART0,
         UART1,
+        SYSTEM,
     }
 }
diff --git a/esp-hal-common/src/peripherals/esp32s3.rs b/esp-hal-common/src/peripherals/esp32s3.rs
@@ -72,5 +72,6 @@ mod peripherals {
         UART1,
         UART2,
         USB_DEVICE,
+        SYSTEM,
     }
 }
diff --git a/esp-hal-common/src/system.rs b/esp-hal-common/src/system.rs
@@ -8,10 +8,12 @@
 //! let system = peripherals.SYSTEM.split();
 //! let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
 //! ```
+
+use crate::peripheral::PeripheralRef;
 #[cfg(not(esp32))]
-type SystemPeripheral = crate::pac::SYSTEM;
+type SystemPeripheral = crate::peripherals::SYSTEM;
 #[cfg(esp32)]
-type SystemPeripheral = crate::pac::DPORT;
+type SystemPeripheral = crate::peripherals::DPORT;
 
 /// Peripherals which can be enabled via [PeripheralClockControl]
 pub enum Peripheral {
@@ -168,8 +170,8 @@ pub struct Dma {
 }
 
 /// The SYSTEM/DPORT splitted into it's different logical parts.
-pub struct SystemParts {
-    _private: (),
+pub struct SystemParts<'d> {
+    _private: PeripheralRef<'d, SystemPeripheral>,
     pub peripheral_clock_control: PeripheralClockControl,
     pub clock_control: SystemClockControl,
     pub cpu_control: CpuControl,
@@ -179,19 +181,19 @@ pub struct SystemParts {
 
 /// Extension trait to split a SYSTEM/DPORT peripheral in independent logical
 /// parts
-pub trait SystemExt {
+pub trait SystemExt<'d> {
     type Parts;
 
     /// Splits the SYSTEM/DPORT peripheral into it's parts.
     fn split(self) -> Self::Parts;
 }
 
-impl SystemExt for SystemPeripheral {
-    type Parts = SystemParts;
+impl<'d, T: crate::peripheral::Peripheral<P = SystemPeripheral> + 'd> SystemExt<'d> for T {
+    type Parts = SystemParts<'d>;
 
     fn split(self) -> Self::Parts {
         Self::Parts {
-            _private: (),
+            _private: self.into_ref(),
             peripheral_clock_control: PeripheralClockControl { _private: () },
             clock_control: SystemClockControl { _private: () },
             cpu_control: CpuControl { _private: () },
-Original file line number
+Diff line change
@@ Expand Up / @@ -61,5 +61,6 @@ mod peripherals { @@
             UART0,
             UART1,
             UART2,
+            DPORT,
         }
     }