Fix I2S for ESP32-C6

esp-hal-common/src/i2s.rs

@@ -1293,6 +1293,7 @@ mod private {
 
     #[cfg(any(esp32c3, esp32c6, esp32s3))]
     pub trait RegisterAccessPrivate: Signals + RegBlock {
+        #[cfg(any(esp32c3, esp32s3))]
         fn set_clock(&self, clock_settings: I2sClockDividers) {
             let i2s = self.register_block();
 
@@ -1392,6 +1393,105 @@ mod private {
             });
         }
 
+        #[cfg(any(esp32c6))]
+        fn set_clock(&self, clock_settings: I2sClockDividers) {
+            let i2s = self.register_block();
+            let pcr = unsafe { &*esp32c6::PCR::PTR }; // I2S clocks are configured via PCR
+
+            let clkm_div_x: u32;
+            let clkm_div_y: u32;
+            let clkm_div_z: u32;
+            let clkm_div_yn1: u32;
+
+            if clock_settings.denominator == 0 || clock_settings.numerator == 0 {
+                clkm_div_x = 0;
+                clkm_div_y = 0;
+                clkm_div_z = 0;
+                clkm_div_yn1 = 1;
+            } else {
+                if clock_settings.numerator > clock_settings.denominator / 2 {
+                    clkm_div_x = clock_settings
+                        .denominator
+                        .overflowing_div(
+                            clock_settings
+                                .denominator
+                                .overflowing_sub(clock_settings.numerator)
+                                .0,
+                        )
+                        .0
+                        .overflowing_sub(1)
+                        .0;
+                    clkm_div_y = clock_settings.denominator
+                        % (clock_settings
+                            .denominator
+                            .overflowing_sub(clock_settings.numerator)
+                            .0);
+                    clkm_div_z = clock_settings
+                        .denominator
+                        .overflowing_sub(clock_settings.numerator)
+                        .0;
+                    clkm_div_yn1 = 1;
+                } else {
+                    clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1;
+                    clkm_div_y = clock_settings.denominator % clock_settings.numerator;
+                    clkm_div_z = clock_settings.numerator;
+                    clkm_div_yn1 = 0;
+                }
+            }
+
+            pcr.i2s_tx_clkm_div_conf.modify(|_, w| {
+                w.i2s_tx_clkm_div_x()
+                    .variant(clkm_div_x as u16)
+                    .i2s_tx_clkm_div_y()
+                    .variant(clkm_div_y as u16)
+                    .i2s_tx_clkm_div_yn1()
+                    .variant(if clkm_div_yn1 != 0 { true } else { false })
+                    .i2s_tx_clkm_div_z()
+                    .variant(clkm_div_z as u16)
+            });
+
+            pcr.i2s_tx_clkm_conf.modify(|_, w| {
+                w.i2s_tx_clkm_en()
+                    .set_bit()
+                    .i2s_tx_clkm_sel()
+                    .variant(2) // for now fixed at 160MHz
+                    .i2s_tx_clkm_div_num()
+                    .variant(clock_settings.mclk_divider as u8)
+            });
+
+            i2s.tx_conf1.modify(|_, w| {
+                w.tx_bck_div_num()
+                    .variant((clock_settings.bclk_divider - 1) as u8)
+            });
+
+            pcr.i2s_rx_clkm_div_conf.modify(|_, w| {
+                w.i2s_rx_clkm_div_x()
+                    .variant(clkm_div_x as u16)
+                    .i2s_rx_clkm_div_y()
+                    .variant(clkm_div_y as u16)
+                    .i2s_rx_clkm_div_yn1()
+                    .variant(if clkm_div_yn1 != 0 { true } else { false })
+                    .i2s_rx_clkm_div_z()
+                    .variant(clkm_div_z as u16)
+            });
+
+            pcr.i2s_rx_clkm_conf.modify(|_, w| {
+                w.i2s_rx_clkm_en()
+                    .set_bit()
+                    .i2s_rx_clkm_sel()
+                    .variant(2) // for now fixed at 160MHz
+                    .i2s_rx_clkm_div_num()
+                    .variant(clock_settings.mclk_divider as u8)
+                    .i2s_mclk_sel()
+                    .variant(true)
+            });
+
+            i2s.rx_conf1.modify(|_, w| {
+                w.rx_bck_div_num()
+                    .variant((clock_settings.bclk_divider - 1) as u8)
+            });
+        }
+
         fn configure(&self, _standard: &Standard, data_format: &DataFormat) {
             let i2s = self.register_block();
             i2s.tx_conf1.modify(|_, w| {