Skip to content

Commit

Permalink
Unify linker scripts (#443)
Browse files Browse the repository at this point in the history
* esp32 & esp32s2 sharing scripts

* add wokwi files

* Add fixup section for esp32s2, fix ordering of sectino includes

* Remove debug asm file

* Use shared linker scripts for s3 with fixups

* Add external.x sections back

* Move ld scripts into esp-hal-common

* esp32c3 unified linker scripts

- rework original c3 script to use the xtensa named sections
  (e.g, _SECTIONNAME_start)
- Add fixups in esp32c3 specific linker
- Remove useless text section start and end (not required when using any
  form of bootloader)

* Add RTC alias'. Move some shared fixups to a file

* comment and cleanup

* unify c2 linker script

* unify c6 linker script

* remove debug configs

* use new esp-riscv-rt

* fmt

* align db symbol names

* fix s3 db
  • Loading branch information
MabezDev authored Mar 20, 2023
1 parent 536adac commit 9a5a546
Show file tree
Hide file tree
Showing 35 changed files with 580 additions and 1,236 deletions.
2 changes: 1 addition & 1 deletion esp-hal-common/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ embassy-time = { version = "0.1.0", features = ["nightly"], optional = tru
embassy-futures = { version = "0.1.0", optional = true }

# RISC-V
esp-riscv-rt = { version = "0.2.0", optional = true }
esp-riscv-rt = { version = "0.3.0", optional = true }
riscv-atomic-emulation-trap = { version = "0.4.0", optional = true }

# Xtensa
Expand Down
20 changes: 20 additions & 0 deletions esp-hal-common/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -150,5 +150,25 @@ fn main() {
fs::copy("ld/xtensa/rom.x", out.join("alias.x")).unwrap();
} else {
fs::copy("ld/riscv/hal-defaults.x", out.join("hal-defaults.x")).unwrap();
fs::copy("ld/riscv/asserts.x", out.join("asserts.x")).unwrap();
fs::copy("ld/riscv/debug.x", out.join("debug.x")).unwrap();
}
copy_dir_all("ld/sections", out).unwrap();
}

fn copy_dir_all(
src: impl AsRef<std::path::Path>,
dst: impl AsRef<std::path::Path>,
) -> std::io::Result<()> {
fs::create_dir_all(&dst)?;
for entry in fs::read_dir(src)? {
let entry = entry?;
let ty = entry.file_type()?;
if ty.is_dir() {
copy_dir_all(entry.path(), dst.as_ref().join(entry.file_name()))?;
} else {
fs::copy(entry.path(), dst.as_ref().join(entry.file_name()))?;
}
}
Ok(())
}
52 changes: 52 additions & 0 deletions esp-hal-common/ld/riscv/asserts.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@


/* Do not exceed this mark in the error messages above | */
ASSERT(ORIGIN(ROTEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the ROTEXT must be 4-byte aligned");

ASSERT(ORIGIN(RODATA) % 4 == 0, "
ERROR(riscv-rt): the start of the RODATA must be 4-byte aligned");

ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");

ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");

ASSERT(ORIGIN(ROTEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the ROTEXT must be 4-byte aligned");

ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");

ASSERT(_stext % 4 == 0, "
ERROR(riscv-rt): `_stext` must be 4-byte aligned");

ASSERT(_data_start % 4 == 0 && _data_end % 4 == 0, "
BUG(riscv-rt): .data is not 4-byte aligned");

ASSERT(_sidata % 4 == 0, "
BUG(riscv-rt): the LMA of .data is not 4-byte aligned");

ASSERT(_bss_start % 4 == 0 && _bss_end % 4 == 0, "
BUG(riscv-rt): .bss is not 4-byte aligned");

ASSERT(_sheap % 4 == 0, "
BUG(riscv-rt): start of .heap is not 4-byte aligned");

ASSERT(_stext + SIZEOF(.text) < ORIGIN(ROTEXT) + LENGTH(ROTEXT), "
ERROR(riscv-rt): The .text section must be placed inside the ROTEXT region.
Set _stext to an address smaller than 'ORIGIN(ROTEXT) + LENGTH(ROTEXT)'");

ASSERT(SIZEOF(.stack) > (_max_hart_id + 1) * _hart_stack_size, "
ERROR(riscv-rt): .stack section is too small for allocating stacks for all the harts.
Consider changing `_max_hart_id` or `_hart_stack_size`.");

ASSERT(SIZEOF(.got) == 0, "
.got section detected in the input files. Dynamic relocations are not
supported. If you are linking to C code compiled using the `gcc` crate
then modify your build script to compile the C code _without_ the
-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
details.");

/* Do not exceed this mark in the error messages above | */
6 changes: 6 additions & 0 deletions esp-hal-common/ld/riscv/debug.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@


SECTIONS {
.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
}
35 changes: 35 additions & 0 deletions esp-hal-common/ld/sections/external.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@


SECTIONS {
.external.data :
{
_external_data_start = ABSOLUTE(.);
. = ALIGN(4);
*(.external.data .external.data.*)
_external_data_end = ABSOLUTE(.);
} > psram_seg AT > RODATA

.external.bss (NOLOAD) :
{
_external_bss_start = ABSOLUTE(.);
. = ALIGN(4);
*(.external.bss .external.bss.*)
_external_bss_end = ABSOLUTE(.);
} > psram_seg

.external.noinit (NOLOAD) :
{
. = ALIGN(4);
*(.external.noinit .external.noinit.*)
} > psram_seg

/* must be last segment using psram_seg */
.external_heap_start (NOLOAD) :
{
. = ALIGN (4);
_external_heap_start = ABSOLUTE(.);
} > psram_seg
}

_external_ram_start = ABSOLUTE(ORIGIN(psram_seg));
_external_ram_end = ABSOLUTE(ORIGIN(psram_seg)+LENGTH(psram_seg));
27 changes: 27 additions & 0 deletions esp-hal-common/ld/sections/fixups/rodata_dummy.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@



SECTIONS {
.rodata_dummy (NOLOAD) :
{
/* This dummy section represents the .flash.text section but in RODATA.
* Thus, it must have its alignment and (at least) its size.
*/

/* Start at the same alignment constraint than .flash.text */

. = ALIGN(ALIGNOF(.text));

/* Create an empty gap as big as .text section */

. = SIZEOF(.text);

/* Prepare the alignment of the section above. Few bytes (0x20) must be
* added for the mapping header.
*/

. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > RODATA
}
INSERT BEFORE .rodata;
14 changes: 14 additions & 0 deletions esp-hal-common/ld/sections/fixups/rtc_fast_rwdata_dummy.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
/*
This fix up is required when the RTC fast memory is split across two address spaces.
This fix up pads the _data bus_ address space by the size of the code accessed by the instruction bus.
*/

SECTIONS {
.rtc_fast.dummy (NOLOAD) :
{
_rtc_dummy_start = ABSOLUTE(.); /* needed to make section proper size */
. = SIZEOF(.rtc_fast.text);
_rtc_dummy_end = ABSOLUTE(.); /* needed to make section proper size */
} > RTC_FAST_RWDATA
}
INSERT BEFORE .rtc_fast.data;
17 changes: 17 additions & 0 deletions esp-hal-common/ld/sections/rodata.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@


SECTIONS {
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
. = ALIGN (4);
*(.rodata .rodata.*)
_rodata_end = ABSOLUTE(.);
} > RODATA

.rodata.wifi :
{
. = ALIGN(4);
*( .rodata_wlog_*.* )
} > RODATA
}
30 changes: 30 additions & 0 deletions esp-hal-common/ld/sections/rtc_fast.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@


SECTIONS {
.rtc_fast.text : {
. = ALIGN(4);
*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
} > RTC_FAST_RWTEXT AT > RODATA

.rtc_fast.data :
{
. = ALIGN(4);
_rtc_fast_data_start = ABSOLUTE(.);
*(.rtc_fast.data .rtc_fast.data.*)
_rtc_fast_data_end = ABSOLUTE(.);
} > RTC_FAST_RWDATA AT > RODATA

.rtc_fast.bss (NOLOAD) :
{
. = ALIGN(4);
_rtc_fast_bss_start = ABSOLUTE(.);
*(.rtc_fast.bss .rtc_fast.bss.*)
_rtc_fast_bss_end = ABSOLUTE(.);
} > RTC_FAST_RWDATA

.rtc_fast.noinit (NOLOAD) :
{
. = ALIGN(4);
*(.rtc_fast.noinit .rtc_fast.noinit.*)
} > RTC_FAST_RWDATA
}
30 changes: 30 additions & 0 deletions esp-hal-common/ld/sections/rtc_slow.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@


SECTIONS {
.rtc_slow.text : {
. = ALIGN(4);
*(.rtc_slow.literal .rtc_slow.text .rtc_slow.literal.* .rtc_slow.text.*)
} > rtc_slow_seg AT > RODATA

.rtc_slow.data :
{
. = ALIGN(4);
_rtc_slow_data_start = ABSOLUTE(.);
*(.rtc_slow.data .rtc_slow.data.*)
_rtc_slow_data_end = ABSOLUTE(.);
} > rtc_slow_seg AT > RODATA

.rtc_slow.bss (NOLOAD) :
{
. = ALIGN(4);
_rtc_slow_bss_start = ABSOLUTE(.);
*(.rtc_slow.bss .rtc_slow.bss.*)
_rtc_slow_bss_end = ABSOLUTE(.);
} > rtc_slow_seg

.rtc_slow.noinit (NOLOAD) :
{
. = ALIGN(4);
*(.rtc_slow.noinit .rtc_slow.noinit.*)
} > rtc_slow_seg
}
55 changes: 55 additions & 0 deletions esp-hal-common/ld/sections/rwdata.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,55 @@


SECTIONS {
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
. = ALIGN (4);
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
*(.data1)
_data_end = ABSOLUTE(.);
} > RWDATA AT > RODATA

/* LMA of .data */
_sidata = LOADADDR(.data);

.bss (NOLOAD) : ALIGN(4)
{
_bss_start = ABSOLUTE(.);
. = ALIGN (4);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.sbss .sbss.* .bss .bss.*);
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
_bss_end = ABSOLUTE(.);
} > RWDATA

.noinit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
*(.noinit .noinit.*)
} > RWDATA

.data.wifi :
{
. = ALIGN(4);
*( .dram1 .dram1.*)
} > RWDATA AT > RODATA

/* must be last segment using RWDATA */
.heap_start (NOLOAD) : ALIGN(4)
{
. = ALIGN (4);
_heap_start = ABSOLUTE(.);
} > RWDATA
}
20 changes: 20 additions & 0 deletions esp-hal-common/ld/sections/rwtext.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@


SECTIONS {
.rwtext : ALIGN(4)
{
. = ALIGN (4);
*(.rwtext.literal .rwtext .rwtext.literal.* .rwtext.*)
} > RWTEXT

.rwtext.wifi :
{
. = ALIGN(4);
*( .wifi0iram .wifi0iram.*)
*( .wifirxiram .wifirxiram.*)
*( .wifislprxiram .wifislprxiram.*)
*( .wifislpiram .wifislpiram.*)
*( .phyiram .phyiram.*)
*( .iram1 .iram1.*)
} > RWTEXT AT > RODATA
}
10 changes: 10 additions & 0 deletions esp-hal-common/ld/sections/text.x
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@


SECTIONS {

.text : ALIGN(4)
{
*(.literal .text .literal.* .text.*)
} > ROTEXT

}
2 changes: 2 additions & 0 deletions esp-hal-common/ld/xtensa/rom.x
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,5 @@ REGION_ALIAS("ROTEXT", irom_seg);
REGION_ALIAS("RWTEXT", iram_seg);
REGION_ALIAS("RODATA", drom_seg);
REGION_ALIAS("RWDATA", dram_seg);
REGION_ALIAS("RTC_FAST_RWTEXT", rtc_fast_iram_seg);
REGION_ALIAS("RTC_FAST_RWDATA", rtc_fast_dram_seg);
Loading

0 comments on commit 9a5a546

Please sign in to comment.