Fmt + clippy + changelog

esp-rs · May 5, 2024 · c5eea25 · c5eea25
1 parent 9613df7
commit c5eea25
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Showing 8 changed files with 92 additions and 32 deletions.
diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `time::current_time` API (#1503)
 - ESP32-S3: Add LCD_CAM Camera driver (#1483)
 - `embassy-usb` support (#1517)
+- Feature: correct `TRNG` mechanism #1804
 
 ### Fixed
 

diff --git a/esp-hal/src/rng.rs b/esp-hal/src/rng.rs
@@ -155,7 +155,7 @@ impl<'d> Trng<'d> {
     ) -> Self {
         let gen = Rng::new(rng);
         crate::soc::trng::ensure_randomness();
-        Self { rng: gen, adc: adc }
+        Self { rng: gen, adc }
     }
 
     pub fn random(&mut self) -> u32 {

diff --git a/esp-hal/src/soc/esp32/trng.rs b/esp-hal/src/soc/esp32/trng.rs
@@ -138,8 +138,7 @@ pub fn ensure_randomness() {
     set_peri_reg_mask(DR_REG_I2S_BASE + 0x00a8, I2S_RX_START);
 }
 
-pub fn revert_trng()
-{
+pub fn revert_trng() {
     clear_peri_reg_mask(I2S_CONF_REG0, I2S_RX_START);
     set_peri_reg_mask(I2S_CONF_REG0, I2S_RX_RESET);
     clear_peri_reg_mask(I2S_CONF_REG0, I2S_RX_RESET);
@@ -152,11 +151,24 @@ pub fn revert_trng()
     clear_peri_reg_mask(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
 
     clear_peri_reg_mask(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
-    clear_peri_reg_mask(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
+    clear_peri_reg_mask(
+        SYSCON_SARADC_CTRL_REG,
+        SYSCON_SARADC_SAR2_MUX | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S,
+    );
 
-    set_peri_reg_bits(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
+    set_peri_reg_bits(
+        SENS_SAR_MEAS_WAIT2_REG,
+        SENS_FORCE_XPD_SAR,
+        0,
+        SENS_FORCE_XPD_SAR_S,
+    );
 
-    set_peri_reg_bits(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
+    set_peri_reg_bits(
+        SYSCON_SARADC_FSM_REG,
+        SYSCON_SARADC_START_WAIT,
+        8,
+        SYSCON_SARADC_START_WAIT_S,
+    );
 }
 
 fn set_peri_reg_bits(reg: u32, bitmap: u32, value: u32, shift: u32) {
@@ -183,4 +195,4 @@ fn write_peri_reg(reg: u32, val: u32) {
     unsafe {
         (reg as *mut u32).write_volatile(val);
     }
-}
+}
diff --git a/esp-hal/src/soc/esp32c2/trng.rs b/esp-hal/src/soc/esp32c2/trng.rs
@@ -173,11 +173,31 @@ pub(crate) fn revert_trng() {
     regi2c_write_mask!(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
     clear_peri_reg_mask(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
     clear_peri_reg_mask(APB_SARADC_DMA_CONF_REG, APB_SARADC_APB_ADC_TRANS_M);
-    reg_set_field(APB_SARADC_SAR_PATT_TAB1_REG, APB_SARADC_SAR_PATT_TAB1_V, APB_SARADC_SAR_PATT_TAB1_S, 0xffffff);
-    reg_set_field(APB_SARADC_SAR_PATT_TAB2_REG, APB_SARADC_SAR_PATT_TAB2_V, APB_SARADC_SAR_PATT_TAB2_S, 0xffffff);
+    reg_set_field(
+        APB_SARADC_SAR_PATT_TAB1_REG,
+        APB_SARADC_SAR_PATT_TAB1_V,
+        APB_SARADC_SAR_PATT_TAB1_S,
+        0xffffff,
+    );
+    reg_set_field(
+        APB_SARADC_SAR_PATT_TAB2_REG,
+        APB_SARADC_SAR_PATT_TAB2_V,
+        APB_SARADC_SAR_PATT_TAB2_S,
+        0xffffff,
+    );
     clear_peri_reg_mask(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M);
-    reg_set_field(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE_V, APB_SARADC_XPD_SAR_FORCE_S, 0);
-    reg_set_field(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR_V, RTC_CNTL_FORCE_XPD_SAR_S, 0);
+    reg_set_field(
+        APB_SARADC_CTRL_REG,
+        APB_SARADC_XPD_SAR_FORCE_V,
+        APB_SARADC_XPD_SAR_FORCE_S,
+        0,
+    );
+    reg_set_field(
+        RTC_CNTL_SENSOR_CTRL_REG,
+        RTC_CNTL_FORCE_XPD_SAR_V,
+        RTC_CNTL_FORCE_XPD_SAR_S,
+        0,
+    );
 }
 
 fn reg_set_field(reg: u32, field_v: u32, field_s: u32, value: u32) {

diff --git a/esp-hal/src/soc/esp32c3/trng.rs b/esp-hal/src/soc/esp32c3/trng.rs
@@ -170,17 +170,37 @@ pub(crate) fn ensure_randomness() {
 }
 
 pub(crate) fn revert_trng() {
-    /* Restore internal I2C bus state */
+    // Restore internal I2C bus state
     regi2c_write_mask!(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
 
-    /* Restore SARADC to default mode */
+    // Restore SARADC to default mode
     clear_peri_reg_mask(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
     clear_peri_reg_mask(APB_SARADC_DMA_CONF_REG, APB_SARADC_APB_ADC_TRANS_M);
-    reg_set_field(APB_SARADC_SAR_PATT_TAB1_REG, APB_SARADC_SAR_PATT_TAB1_V, APB_SARADC_SAR_PATT_TAB1_S, 0xffffff);
-    reg_set_field(APB_SARADC_SAR_PATT_TAB2_REG, APB_SARADC_SAR_PATT_TAB2_V, APB_SARADC_SAR_PATT_TAB2_S, 0xffffff);
+    reg_set_field(
+        APB_SARADC_SAR_PATT_TAB1_REG,
+        APB_SARADC_SAR_PATT_TAB1_V,
+        APB_SARADC_SAR_PATT_TAB1_S,
+        0xffffff,
+    );
+    reg_set_field(
+        APB_SARADC_SAR_PATT_TAB2_REG,
+        APB_SARADC_SAR_PATT_TAB2_V,
+        APB_SARADC_SAR_PATT_TAB2_S,
+        0xffffff,
+    );
     clear_peri_reg_mask(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M);
-    reg_set_field(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE_V, APB_SARADC_XPD_SAR_FORCE_S, 0);
-    reg_set_field(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR_V, RTC_CNTL_FORCE_XPD_SAR_S, 0);
+    reg_set_field(
+        APB_SARADC_CTRL_REG,
+        APB_SARADC_XPD_SAR_FORCE_V,
+        APB_SARADC_XPD_SAR_FORCE_S,
+        0,
+    );
+    reg_set_field(
+        RTC_CNTL_SENSOR_CTRL_REG,
+        RTC_CNTL_FORCE_XPD_SAR_V,
+        RTC_CNTL_FORCE_XPD_SAR_S,
+        0,
+    );
 }
 
 fn reg_set_field(reg: u32, field_v: u32, field_s: u32, value: u32) {
@@ -202,4 +222,4 @@ fn clear_peri_reg_mask(reg: u32, mask: u32) {
     unsafe {
         (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !mask);
     }
-}
+}
diff --git a/esp-hal/src/soc/esp32h2/trng.rs b/esp-hal/src/soc/esp32h2/trng.rs
@@ -243,7 +243,7 @@ pub(crate) fn revert_trng() {
         I2C_SARADC_SAR2_INIT_CODE_LSB_LSB,
         0,
     );
-    
+
     regi2c_write_mask(
         I2C_SAR_ADC,
         I2C_SAR_ADC_HOSTID,
@@ -291,7 +291,7 @@ pub(crate) fn revert_trng() {
 
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     reg_write(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
-    
+
     // Set PCR_SARADC_CONF_REG to initial state
     reg_write(PCR_SARADC_CONF_REG, 0x5);
 }

diff --git a/esp-hal/src/soc/esp32s2/trng.rs b/esp-hal/src/soc/esp32s2/trng.rs
@@ -196,16 +196,15 @@ pub(crate) fn ensure_randomness() {
     set_peri_reg_mask(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
 }
 
-pub fn revert_trng()
-{
+pub fn revert_trng() {
     // Restore internal I2C bus state
     regi2c_write_mask(
         I2C_SAR_ADC,
         I2C_SAR_ADC_HOSTID,
         ADC_SAR1_DREF_ADDR,
         ADC_SAR1_DREF_ADDR_MSB,
         ADC_SAR1_DREF_ADDR_LSB,
-        0x1
+        0x1,
     );
 
     regi2c_write_mask(
@@ -214,7 +213,7 @@ pub fn revert_trng()
         ADC_SAR2_DREF_ADDR,
         ADC_SAR2_DREF_ADDR_MSB,
         ADC_SAR2_DREF_ADDR_LSB,
-        0x1
+        0x1,
     );
 
     regi2c_write_mask(
@@ -247,7 +246,12 @@ pub fn revert_trng()
     // Restore SARADC to default mode
     clear_peri_reg_mask(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
     set_peri_reg_mask(DPORT_PERIP_CLK_EN0_REG, DPORT_APB_SARADC_CLK_EN);
-    set_peri_reg_bits(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
+    set_peri_reg_bits(
+        SENS_SAR_POWER_XPD_SAR_REG,
+        SENS_FORCE_XPD_SAR,
+        0,
+        SENS_FORCE_XPD_SAR_S,
+    );
     clear_peri_reg_mask(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
 }
 
@@ -370,8 +374,7 @@ fn set_peri_reg_mask(reg: u32, mask: u32) {
 fn set_peri_reg_bits(reg: u32, bitmap: u32, value: u32, shift: u32) {
     unsafe {
         (reg as *mut u32).write_volatile(
-            ((reg as *mut u32).read_volatile() & !(bitmap << shift))
-                | ((value & bitmap) << shift),
+            ((reg as *mut u32).read_volatile() & !(bitmap << shift)) | ((value & bitmap) << shift),
         );
     }
 }
@@ -386,4 +389,4 @@ fn write_peri_reg(reg: u32, val: u32) {
     unsafe {
         (reg as *mut u32).write_volatile(val);
     }
-}
+}
diff --git a/esp-hal/src/soc/esp32s3/trng.rs b/esp-hal/src/soc/esp32s3/trng.rs
@@ -183,8 +183,7 @@ pub(crate) fn ensure_randomness() {
     regi2c_write_mask!(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
 }
 
-pub fn revert_trng()
-{
+pub fn revert_trng() {
     regi2c_write_mask!(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0);
 
     regi2c_write_mask!(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
@@ -193,7 +192,12 @@ pub fn revert_trng()
 
     regi2c_write_mask!(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
 
-    reg_set_field(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR_V, SENS_FORCE_XPD_SAR_S, 0);
+    reg_set_field(
+        SENS_SAR_POWER_XPD_SAR_REG,
+        SENS_FORCE_XPD_SAR_V,
+        SENS_FORCE_XPD_SAR_S,
+        0,
+    );
 
     clear_peri_reg_mask(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
 
@@ -233,4 +237,4 @@ fn write_peri_reg(reg: u32, val: u32) {
     unsafe {
         (reg as *mut u32).write_volatile(val);
     }
-}
+}