Properly update the Uart config in examples (#1759)

* fix: Properly update the config * feat: Make rx_timeout optional * docs: Update changelog
esp-rs · Jul 8, 2024 · ea34196 · ea34196
1 parent 967c478
commit ea34196
Show file tree

Hide file tree

Showing 4 changed files with 7 additions and 8 deletions.
diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add support for GPIO wake-up source (#1724)
 - dma: add Mem2Mem to support memory to memory transfer (#1738)
 - Add `uart` wake source (#1727)
+- uart: Make `rx_timeout` optional in Config struct (#1759)
 
 ### Fixed
 

diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
@@ -274,7 +274,7 @@ pub mod config {
  pub stop_bits: StopBits,
  pub clock_source: super::ClockSource,
  pub rx_fifo_full_threshold: u16,
- pub rx_timeout: u8,
+ pub rx_timeout: Option<u8>,
  }
 
  impl Config {
@@ -337,7 +337,7 @@ pub mod config {
  self
  }
 
- pub fn rx_timeout(mut self, timeout: u8) -> Self {
+ pub fn rx_timeout(mut self, timeout: Option<u8>) -> Self {
  self.rx_timeout = timeout;
  self
  }
@@ -355,7 +355,7 @@ pub mod config {
  #[cfg(not(any(esp32c6, esp32h2, lp_uart)))]
  clock_source: super::ClockSource::Apb,
  rx_fifo_full_threshold: UART_FULL_THRESH_DEFAULT,
- rx_timeout: UART_TOUT_THRESH_DEFAULT,
+ rx_timeout: Some(UART_TOUT_THRESH_DEFAULT),
  }
  }
  }
@@ -764,7 +764,7 @@ where
  serial
  .rx
  .set_rx_fifo_full_threshold(config.rx_fifo_full_threshold)?;
- serial.rx.set_rx_timeout(Some(config.rx_timeout))?;
+ serial.rx.set_rx_timeout(config.rx_timeout)?;
  serial.change_baud_internal(config.baudrate, config.clock_source, clocks);
  serial.change_data_bits(config.data_bits);
  serial.change_parity(config.parity);

diff --git a/examples/src/bin/embassy_serial.rs b/examples/src/bin/embassy_serial.rs
@@ -106,8 +106,7 @@ async fn main(spawner: Spawner) {
  #[cfg(feature = "esp32s3")]
  let (tx_pin, rx_pin) = (io.pins.gpio43, io.pins.gpio44);
 
- let config = Config::default();
- config.rx_fifo_full_threshold(READ_BUF_SIZE as u16);
+ let config = Config::default().rx_fifo_full_threshold(READ_BUF_SIZE as u16);
 
  let mut uart0 =
  Uart::new_async_with_config(peripherals.UART0, config, &clocks, tx_pin, rx_pin).unwrap();

diff --git a/examples/src/bin/serial_interrupts.rs b/examples/src/bin/serial_interrupts.rs
@@ -52,8 +52,7 @@ fn main() -> ! {
  let (tx_pin, rx_pin) = (io.pins.gpio43, io.pins.gpio44);
  #[cfg(feature = "esp32s3")]
  let (tx_pin, rx_pin) = (io.pins.gpio43, io.pins.gpio44);
- let config = Config::default();
- config.rx_fifo_full_threshold(30);
+ let config = Config::default().rx_fifo_full_threshold(30);
 
  let mut uart0 = Uart::new_with_config(
  peripherals.UART0,