SPI: Implement more SPI traits from embedded-hal 1.0.0-alpha.8 #101
Commits on Aug 17, 2022
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common/spi: Turn fifo size into const
instead of hard-coding it into the code in various places.
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common/spi: Alias
write_bytestosend_bytessince they share the same interface and the same code anyway.
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common/spi: Implement
read_bytesas counterpart to `send_bytes` that is responsible only for reading bytes received via SPI.
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to use `send_bytes` and `read_bytes` under the hood and remove duplicate code.
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common/spi: Create submodule for embedded_hal_1
that is re-exported when the `eh1` feature flag is active. This removes lots of duplicate `#[cfg(...)]` macros previously part of the code.
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common/spi: Implement
SpiBusandSpiBusWritetraits from the `embedded-hal 1.0.0-alpha.8`.
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esp32-hal/examples/spi_eh1: Add huge transfer
and bump the SPI speed to 1 MHz.
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common/spi: Use
memcpyto read from registersThis cuts down the time between consecutive transfers from about 2 ms to less than 1 ms.
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WIP: common/spi: Use
ptr::copyto fill write FIFOcutting down the time between transfers from just below 1 ms to ~370 us. The implementation is currently broken in that it will always fill the entire FIFO from the input it is given, even if that isn't FIFO-sized...
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esp32/examples/spi_eh1: Add conditional compile
and compile a dummy instead when the "eh1" feature isn't present.
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esp32-hal: Ignore spi_eh1 example
in normal builds, where the feature flag "eh1" isn't given. Building the example directly via `cargo build --example spi_eh1_loopback` will now print an error that this requires a feature flag to be active.
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and drop `send_bytes` instead. Previoulsy, both served the same purpose, but `send_bytes` was introduced more recently and is hence less likely to cause breaking changes in existing code.
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The previous `read` implementation would only read the contents of the SPI receive FIFO and return that as data. However, the `SpiBusRead` trait defines that while reading, bytes should be written out to the bus (Because SPI is transactional, without writing nothing can be read). Reimplements the `embedded-hal` traits to correctly implement this behavior.
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common/spi: Use full FIFO size on all variants
All esp variants except for the esp32s2 have a 64 byte FIFO, whereas the esp32s2 has a 72 byte FIFO.
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common/spi: Fix reading bytes from FIFO
by reverting to the old method of reading 32 bytes at a time and assembling the return buffer from that. It turns out that the previous `core::slice::from_raw_parts()` doesn't work for the esp32s2 and esp32s3 variants, returning bogus data even though the correct data is present in the registers.
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