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Combine the esp-ulp-riscv-hal
and esp32c6-lp-hal
packages
#1115
Combine the esp-ulp-riscv-hal
and esp32c6-lp-hal
packages
#1115
Conversation
This is true now but do the other peripherals the similar registers between the lp and ulp? I was planning on contributing some drivers to |
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LGTM
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I think we should also update the general README https://github.com/esp-rs/esp-hal?tab=readme-ov-file#low-power-cores
I think contributing just for the targets you can test is totally fine I was a bit afraid of merging the HALs, too. Especially for upcoming features which are very different for different the targets (especially interrupt handling) - but on the other hand in esp-hal-common we even target two different architectures |
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LGTM, thanks for working on this!
The S2/S3 ULPs have like 4 peripherals, most of which are already covered or in-progress. The C6 (and soon, the P4) have very similar LP cores with very similar peripherals. These cores are more similar than a lot of the HP cores in
We have never required people implement drivers for all supported devices, we have multiple drivers in |
Since we're planning on combining the HAL packages for the HP cores, makes sense to do the same for the LP cores, IMO. There was a fair bit of overlap in the implementations of the GPIO and Delay drivers, so we've been able to eliminate some code there. For the parts that are different, we can just
#[cfg()]
them off as needed like we already do inesp-hal-common
.I've also implemented the
embedded-hal@1.0.0
traits in addition to the0.2.x
traits; both of which can be enabled/disable using features. I have enabledembedded-hal@0.2.x
by default for now, because those were the traits which had previously already been implemented, but maybe we want to change this? Anyway, not a huge issue, but something to be aware of.If anybody has any input regarding the package name or any other implementation details, please let me know!