critical_section implementations & esp_backtrace

.github/workflows/ci.yml

@@ -118,7 +118,7 @@ jobs:
         with:
           profile: minimal
           target: riscv32imc-unknown-none-elf
-          toolchain: "1.59.0"
+          toolchain: "1.60.0"
           default: true
       - uses: Swatinem/rust-cache@v1
       - uses: actions-rs/cargo@v1
@@ -140,7 +140,7 @@ jobs:
           default: true
           ldproxy: false
           buildtargets: ${{ matrix.chip }}
-          version: "1.59.0"
+          version: "1.60.0"
       - uses: Swatinem/rust-cache@v1
       - uses: actions-rs/cargo@v1
         with:

README.md

@@ -36,8 +36,8 @@ _\* via [atomic emulation]_
 
 The **M**inimum **S**upported **R**ust **V**ersions are:
 
-- `1.59.0` for RISC-V devices (**ESP32-C3**)
-- `1.59.0` for Xtensa devices (**ESP32**, **ESP32-S2**, **ESP32-S3**)
+- `1.60.0` for RISC-V devices (**ESP32-C3**)
+- `1.60.0` for Xtensa devices (**ESP32**, **ESP32-S2**, **ESP32-S3**)
 
 Note that targeting the Xtensa ISA requires the use of the [esp-rs/rust] compiler fork, whereas RISC-V is officially supported by the official Rust compiler.
 

esp-hal-common/Cargo.toml

@@ -34,6 +34,8 @@ ufmt-write = { version = "0.1", optional = true }
 # Smart-LED (e.g., WS2812/SK68XX) support
 smart-leds-trait = { version = "0.2.1", optional = true }
 
+critical-section = "1.0.0"
+
 # IMPORTANT:
 # Each supported device MUST have its PAC included below along with a
 # corresponding feature. We rename the PAC packages because we cannot
@@ -46,10 +48,10 @@ esp32s2_pac = { package = "esp32s2", version = "0.3.0",  optional = true }
 esp32s3_pac = { package = "esp32s3", version = "0.3.0",  optional = true }
 
 [features]
-esp32   = ["esp32_pac/rt"  , "procmacros/xtensa", "multi_core" , "xtensa-lx-rt/esp32",   "xtensa-lx/esp32"]
-esp32c3 = ["esp32c3_pac/rt", "procmacros/riscv" , "single_core", "riscv", "riscv-atomic-emulation-trap"]
-esp32s2 = ["esp32s2_pac/rt", "procmacros/xtensa", "single_core", "xtensa-lx-rt/esp32s2", "xtensa-lx/esp32s2"]
-esp32s3 = ["esp32s3_pac/rt", "procmacros/xtensa", "multi_core" , "xtensa-lx-rt/esp32s3", "xtensa-lx/esp32s3"]
+esp32   = ["esp32_pac/rt"  , "procmacros/xtensa", "multi_core" , "xtensa-lx-rt/esp32",   "xtensa-lx/esp32",   "critical-section/restore-state-u32"]
+esp32c3 = ["esp32c3_pac/rt", "procmacros/riscv" , "single_core", "riscv", "riscv-atomic-emulation-trap",      "critical-section/restore-state-u8"]
+esp32s2 = ["esp32s2_pac/rt", "procmacros/xtensa", "single_core", "xtensa-lx-rt/esp32s2", "xtensa-lx/esp32s2", "critical-section/restore-state-u32"]
+esp32s3 = ["esp32s3_pac/rt", "procmacros/xtensa", "multi_core" , "xtensa-lx-rt/esp32s3", "xtensa-lx/esp32s3", "critical-section/restore-state-u32"]
 
 # Core Count (should not be enabled directly, but instead by a PAC's feature)
 single_core = []

esp-hal-common/src/clocks_ll/esp32.rs

@@ -1,8 +1,4 @@
-use crate::clock::{
-    Clock,
-    XtalClock,
-    PllClock,
-};
+use crate::clock::{Clock, PllClock, XtalClock};
 
 const REF_CLK_FREQ: u32 = 1000000;
 

esp-hal-common/src/clocks_ll/esp32c3.rs

@@ -1,9 +1,11 @@
 use paste::paste;
 
-use crate::clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock};
-
-use crate::rom::{ets_update_cpu_frequency, regi2c_ctrl_write_reg, regi2c_ctrl_write_reg_mask};
-use crate::{regi2c_write, regi2c_write_mask};
+use crate::{
+    clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock},
+    regi2c_write,
+    regi2c_write_mask,
+    rom::{ets_update_cpu_frequency, regi2c_ctrl_write_reg, regi2c_ctrl_write_reg_mask},
+};
 
 const I2C_BBPLL: u32 = 0x66;
 const I2C_BBPLL_HOSTID: u32 = 0;
@@ -188,7 +190,8 @@ pub(crate) fn esp32c3_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
 
     unsafe {
         ets_update_cpu_frequency(freq.mhz());
-        // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first.
+        // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0)
+        // first.
         system_control.sysclk_conf.modify(|_, w| {
             w.pre_div_cnt()
                 .bits(0)

esp-hal-common/src/gpio.rs

@@ -142,8 +142,9 @@ pub trait InputPin: Pin {
 
     /// Remove a connected `signal` from this input pin.
     ///
-    /// Clears the entry in the GPIO matrix / IO mux that associates this input pin with the given
-    /// [input `signal`](`InputSignal`). Any other connected signals remain intact.
+    /// Clears the entry in the GPIO matrix / IO mux that associates this input
+    /// pin with the given [input `signal`](`InputSignal`). Any other
+    /// connected signals remain intact.
     fn disconnect_input_from_peripheral(&mut self, signal: InputSignal) -> &mut Self;
 }
 
@@ -181,9 +182,9 @@ pub trait OutputPin: Pin {
 
     /// Remove this output pin from a connected [signal](`InputSignal`).
     ///
-    /// Clears the entry in the GPIO matrix / IO mux that associates this output pin with a
-    /// previously connected [signal](`InputSignal`). Any other outputs connected to the signal
-    /// remain intact.
+    /// Clears the entry in the GPIO matrix / IO mux that associates this output
+    /// pin with a previously connected [signal](`InputSignal`). Any other
+    /// outputs connected to the signal remain intact.
     fn disconnect_peripheral_from_output(&mut self) -> &mut Self;
 
     fn internal_pull_up(&mut self, on: bool) -> &mut Self;

esp-hal-common/src/ledc/timer.rs

@@ -161,7 +161,8 @@ where
         let mut divisor = ((src_freq as u64) << 8) / frequency as u64 / precision as u64;
 
         if divisor > LEDC_TIMER_DIV_NUM_MAX {
-            // APB_CLK results in divisor which too high. Try using REF_TICK as clock source.
+            // APB_CLK results in divisor which too high. Try using REF_TICK as clock
+            // source.
             self.use_ref_tick = true;
             divisor = ((1_000_000 as u64) << 8) / frequency as u64 / precision as u64;
         }

esp-hal-common/src/lib.rs

@@ -17,6 +17,7 @@
 //! [esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal
 
 #![no_std]
+#![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))]
 
 #[cfg(feature = "esp32")]
 pub use esp32_pac as pac;
@@ -101,3 +102,120 @@ pub fn get_core() -> Cpu {
     #[cfg(feature = "single_core")]
     Cpu::ProCpu
 }
+
+mod critical_section_impl {
+    struct CriticalSection;
+
+    critical_section::set_impl!(CriticalSection);
+
+    #[cfg(target_arch = "xtensa")]
+    mod xtensa {
+
+        unsafe impl critical_section::Impl for super::CriticalSection {
+            unsafe fn acquire() -> critical_section::RawRestoreState {
+                let tkn: critical_section::RawRestoreState;
+                core::arch::asm!("rsil {0}, 15", out(reg) tkn);
+                #[cfg(feature = "multicore")]
+                {
+                    let guard = multicore::MULTICORE_LOCK.lock();
+                    core::mem::forget(guard); // forget it so drop doesn't run
+                }
+                tkn
+            }
+
+            unsafe fn release(token: critical_section::RawRestoreState) {
+                if token != 0 {
+                    #[cfg(feature = "multicore")]
+                    {
+                        debug_assert!(multicore::MULTICORE_LOCK.is_owned_by_current_thread());
+                        // safety: we logically own the mutex from acquire()
+                        multicore::MULTICORE_LOCK.force_unlock();
+                    }
+                    core::arch::asm!(
+                        "wsr.ps {0}",
+                        "rsync", in(reg) token)
+                }
+            }
+        }
+    }
+
+    #[cfg(target_arch = "riscv32")]
+    mod riscv {
+        unsafe impl critical_section::Impl for super::CriticalSection {
+            unsafe fn acquire() -> critical_section::RawRestoreState {
+                let interrupts_active = riscv::register::mstatus::read().mie();
+                riscv::interrupt::disable();
+
+                #[cfg(feature = "multicore")]
+                {
+                    let guard = multicore::MULTICORE_LOCK.lock();
+                    core::mem::forget(guard); // forget it so drop doesn't run
+                }
+
+                interrupts_active as _
+            }
+
+            unsafe fn release(token: critical_section::RawRestoreState) {
+                if token != 0 {
+                    #[cfg(feature = "multicore")]
+                    {
+                        debug_assert!(multicore::MULTICORE_LOCK.is_owned_by_current_thread());
+                        // safety: we logically own the mutex from acquire()
+                        multicore::MULTICORE_LOCK.force_unlock();
+                    }
+                    riscv::interrupt::enable();
+                }
+            }
+        }
+    }
+
+    #[cfg(feature = "multicore")]
+    mod multicore {
+        use core::sync::atomic::{AtomicBool, Ordering};
+
+        use lock_api::{GetThreadId, GuardSend, RawMutex};
+
+        use crate::get_core;
+
+        /// Reentrant Mutex
+        ///
+        /// Currently implemented using an atomic spin lock.
+        /// In the future we can optimize this raw mutex to use some hardware
+        /// features.
+        pub(crate) static MULTICORE_LOCK: lock_api::ReentrantMutex<RawSpinlock, RawThreadId, ()> =
+            lock_api::ReentrantMutex::const_new(RawSpinlock::INIT, RawThreadId::INIT, ());
+
+        pub(crate) struct RawThreadId;
+
+        unsafe impl lock_api::GetThreadId for RawThreadId {
+            const INIT: Self = RawThreadId;
+
+            fn nonzero_thread_id(&self) -> core::num::NonZeroUsize {
+                core::num::NonZeroUsize::new((get_core() as usize) + 1).unwrap()
+            }
+        }
+
+        pub(crate) struct RawSpinlock(AtomicBool);
+
+        unsafe impl lock_api::RawMutex for RawSpinlock {
+            const INIT: RawSpinlock = RawSpinlock(AtomicBool::new(false));
+
+            // A spinlock guard can be sent to another thread and unlocked there
+            type GuardMarker = GuardSend;
+
+            fn lock(&self) {
+                while !self.try_lock() {}
+            }
+
+            fn try_lock(&self) -> bool {
+                self.0
+                    .compare_exchange(false, true, Ordering::Acquire, Ordering::Relaxed)
+                    .is_ok()
+            }
+
+            unsafe fn unlock(&self) {
+                self.0.store(false, Ordering::Release);
+            }
+        }
+    }
+}

esp-hal-common/src/rtc/esp32.rs

@@ -1,6 +1,8 @@
-use crate::{clock::XtalClock, pac::RTC_CNTL};
-
-use crate::rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock};
+use crate::{
+    clock::XtalClock,
+    pac::RTC_CNTL,
+    rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
+};
 
 pub(crate) fn init() {}
 

esp-hal-common/src/rtc/esp32c3.rs

@@ -1,14 +1,13 @@
 use paste::paste;
 
 use crate::{
-    clock::XtalClock, pac::APB_CTRL, pac::EXTMEM, pac::RTC_CNTL, pac::SPI0, pac::SPI1, pac::SYSTEM,
+    clock::XtalClock,
+    pac::{APB_CTRL, EXTMEM, RTC_CNTL, SPI0, SPI1, SYSTEM},
+    regi2c_write_mask,
+    rom::regi2c_ctrl_write_reg_mask,
+    rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
 };
 
-use crate::rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock};
-
-use crate::regi2c_write_mask;
-use crate::rom::regi2c_ctrl_write_reg_mask;
-
 const I2C_DIG_REG: u32 = 0x6d;
 const I2C_DIG_REG_HOSTID: u32 = 0;
 

esp-hal-common/src/rtc/esp32s2.rs

@@ -1,6 +1,8 @@
-use crate::{clock::XtalClock, pac::RTC_CNTL};
-
-use crate::rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock};
+use crate::{
+    clock::XtalClock,
+    pac::RTC_CNTL,
+    rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
+};
 
 pub(crate) fn init() {}
 

esp-hal-common/src/rtc/esp32s3.rs

@@ -1,6 +1,8 @@
-use crate::{clock::XtalClock, pac::RTC_CNTL};
-
-use crate::rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock};
+use crate::{
+    clock::XtalClock,
+    pac::RTC_CNTL,
+    rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
+};
 
 pub(crate) fn init() {}