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Improve RISC-V interrupt latency #1679
Improve RISC-V interrupt latency #1679
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CI fails because of current |
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LGTM, thanks!
// jr handle_interrupts | ||
// ``` | ||
// | ||
// We can do better manually - use Rust again once/if that changes |
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Tbh, this should have been in asm from the start, I was just lazy & hoped the compiler would show just the smallest amount of intelligence 🥲
#[inline] | ||
fn get_configured_interrupts(core: Cpu, mut status: u128) -> [u128; 16] { | ||
fn get_configured_interrupts( |
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This is a much better way of doing this, nice! We can also apply to Xtensa too, I think there is a very similar block of code. Let's do that in a separate PR though (I'll make a note in the tracking issue).
/// Get status of peripheral interrupts | ||
#[inline] | ||
pub fn get_status(_core: Cpu) -> u128 { | ||
pub fn get_status(_core: Cpu) -> InterruptStatus { |
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I guess we should avoid u128's where possible in general tbh, it seems the codegen for them is not really that good - nice find.
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Thanks, this is a big improvement!
@bjoernQ mind rebasing this when you get the chance? |
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Thank you for your contribution!
We appreciate the time and effort you've put into this pull request.
To help us review it efficiently, please ensure you've gone through the following checklist:
Submission Checklist 📝
cargo xtask fmt-packages
command to ensure that all changed code is formatted correctly.CHANGELOG.md
in the proper section.Extra:
Pull Request Details 📖
Description
This improves interrupt latency on RISC-V based chips.
Testing
All interrupt, embassy and esp-wifi examples still work.
To test the latency, I modified the
gpio_interrupt.rs
example like this:Then use a logic-analyzer triggering on GPIO 9 and measure the time from the falling edge of GPIO 9 to the changing edge on GPIO 2. This obviously includes more than just the time to trigger the interrupt but it's also a somewhat realistic test.
Here is what I measured:
(all measured at boot defaults / 40MHz flash frequency, used rustc 1.80.0-nightly (79734f1db 2024-05-02))
C2
before 31.692 / 12.40
after 18.517 / 5.64
C3
before 21.432 / 10.572
after 11.79 / 4.99
C6
before 17.125 / 10.71
after 8.95 / 5.94
H2
before 25.335 / 11.36
after 14.27 / 5.44
I'm quite happy with the improvement!
The first triggering is still much slower which is because there are cache misses (see #1162 - originally, I wanted to address the things there, will add a comment why I didn't there - see #1162 (comment))
We should probably try something similar for Xtensa