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SYSTIMER peripheral #76

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Jun 10, 2022
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35 changes: 4 additions & 31 deletions esp-hal-common/src/delay.rs
Original file line number Diff line number Diff line change
Expand Up @@ -32,60 +32,33 @@ where
mod delay {
use fugit::HertzU64;

use crate::{clock::Clocks, pac::SYSTIMER};
use crate::{clock::Clocks, systimer::SystemTimer};

/// Uses the `SYSTIMER` peripheral for counting clock cycles, as
/// unfortunately the ESP32-C3 does NOT implement the `mcycle` CSR, which is
/// how we would normally do this.
pub struct Delay {
systimer: SYSTIMER,
freq: HertzU64,
}

impl Delay {
/// Create a new Delay instance
pub fn new(systimer: SYSTIMER, clocks: &Clocks) -> Self {
pub fn new(clocks: &Clocks) -> Self {
// The counters and comparators are driven using `XTAL_CLK`. The average clock
// frequency is fXTAL_CLK/2.5, which is 16 MHz. The timer counting is
// incremented by 1/16 μs on each `CNT_CLK` cycle.

Self {
systimer,
freq: HertzU64::MHz((clocks.xtal_clock.to_MHz() * 10 / 25) as u64),
}
}

/// Return the raw interface to the underlying SYSTIMER instance
pub fn free(self) -> SYSTIMER {
self.systimer
}

/// Delay for the specified number of microseconds
pub fn delay(&self, us: u32) {
let t0 = self.unit0_value();
let t0 = SystemTimer::now();
let clocks = (us as u64 * self.freq.raw()) / HertzU64::MHz(1).raw();

while self.unit0_value().wrapping_sub(t0) <= clocks {}
}

#[inline(always)]
fn unit0_value(&self) -> u64 {
self.systimer
.unit0_op
.write(|w| w.timer_unit0_update().set_bit());

while !self
.systimer
.unit0_op
.read()
.timer_unit0_value_valid()
.bit_is_set()
{}

let value_lo = self.systimer.unit0_value_lo.read().bits();
let value_hi = self.systimer.unit0_value_hi.read().bits();

((value_hi as u64) << 32) | value_lo as u64
while SystemTimer::now().wrapping_sub(t0) <= clocks {}
}
}
}
Expand Down
2 changes: 2 additions & 0 deletions esp-hal-common/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,8 @@ pub use spi::Spi;
pub use timer::Timer;
#[cfg(any(feature = "esp32c3", feature = "esp32s3"))]
pub use usb_serial_jtag::UsbSerialJtag;
#[cfg(any(feature = "esp32c3", feature = "esp32s3", feature = "esp32s2"))]
pub mod systimer;

pub mod clock;
pub mod system;
Expand Down
175 changes: 175 additions & 0 deletions esp-hal-common/src/systimer.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,175 @@
use core::{intrinsics::transmute, marker::PhantomData};

use crate::pac::{
generic::Reg,
systimer::{
target0_conf::TARGET0_CONF_SPEC,
target0_hi::TARGET0_HI_SPEC,
target0_lo::TARGET0_LO_SPEC,
},
SYSTIMER,
};

// TODO this only handles unit0 of the systimer

#[derive(Debug)]
pub struct SystemTimer {
_inner: SYSTIMER,
pub alarm0: Alarm<Target, 0>,
pub alarm1: Alarm<Target, 1>,
pub alarm2: Alarm<Target, 2>,
}

impl SystemTimer {
pub fn new(p: SYSTIMER) -> Self {
Self {
_inner: p,
alarm0: Alarm::new(),
alarm1: Alarm::new(),
alarm2: Alarm::new(),
}
}

// TODO use fugit types
pub fn now() -> u64 {
// This should be safe to access from multiple contexts
// worst case scenario the second accesor ends up reading
// an older time stamp
let systimer = unsafe { &*SYSTIMER::ptr() };
systimer
.unit0_op
.modify(|_, w| w.timer_unit0_update().set_bit());

while !systimer
.unit0_op
.read()
.timer_unit0_value_valid()
.bit_is_set()
{}

let value_lo = systimer.unit0_value_lo.read().bits();
let value_hi = systimer.unit0_value_hi.read().bits();

((value_hi as u64) << 32) | value_lo as u64
}
}

#[derive(Debug)]
pub struct Target;
// pub struct Periodic; // TODO, also impl e-h timer traits

#[derive(Debug)]
pub struct Alarm<MODE, const CHANNEL: u8> {
_pd: PhantomData<MODE>,
}

impl<T, const CHANNEL: u8> Alarm<T, CHANNEL> {
// private constructor
fn new() -> Self {
Self { _pd: PhantomData }
}

pub fn enable_interrupt(&self) {
let systimer = unsafe { &*SYSTIMER::ptr() };
match CHANNEL {
0 => systimer
.int_ena
.modify(|_, w| w.target0_int_ena().set_bit()),
1 => systimer
.int_ena
.modify(|_, w| w.target1_int_ena().set_bit()),
2 => systimer
.int_ena
.modify(|_, w| w.target2_int_ena().set_bit()),
_ => unreachable!(),
}
}

pub fn clear_interrupt(&self) {
let systimer = unsafe { &*SYSTIMER::ptr() };
match CHANNEL {
0 => systimer.int_clr.write(|w| w.target0_int_clr().set_bit()),
1 => systimer.int_clr.write(|w| w.target1_int_clr().set_bit()),
2 => systimer.int_clr.write(|w| w.target2_int_clr().set_bit()),
_ => unreachable!(),
}
}
}

impl<const CHANNEL: u8> Alarm<Target, CHANNEL> {
pub fn set_target(&self, timestamp: u64) {
unsafe {
let systimer = &*SYSTIMER::ptr();
let (tconf, hi, lo): (
&Reg<TARGET0_CONF_SPEC>,
&Reg<TARGET0_HI_SPEC>,
&Reg<TARGET0_LO_SPEC>,
) = match CHANNEL {
0 => (
&systimer.target0_conf,
&systimer.target0_hi,
&systimer.target0_lo,
),
1 => (
transmute(&systimer.target1_conf),
transmute(&systimer.target1_hi),
transmute(&systimer.target1_lo),
),
2 => (
transmute(&systimer.target2_conf),
transmute(&systimer.target2_hi),
transmute(&systimer.target2_lo),
),
_ => unreachable!(),
};

#[cfg(feature = "esp32s2")]
systimer.step.write(|w| w.timer_xtal_step().bits(0x1)); // run at XTAL freq, not 80 * XTAL freq

#[cfg(any(feature = "esp32c3", feature = "esp32s3"))]
{
tconf.write(|w| w.target0_timer_unit_sel().clear_bit()); // default, use unit 0
systimer
.conf
.modify(|_, w| w.timer_unit0_core0_stall_en().clear_bit());
}

tconf.write(|w| w.target0_period_mode().clear_bit()); // target mode
hi.write(|w| w.timer_target0_hi().bits((timestamp >> 32) as u32));
lo.write(|w| w.timer_target0_lo().bits((timestamp & 0xFFFF_FFFF) as u32));

#[cfg(any(feature = "esp32c3", feature = "esp32s3"))]
{
match CHANNEL {
0 => {
systimer
.comp0_load
.write(|w| w.timer_comp0_load().set_bit());
}
1 => systimer
.comp1_load
.write(|w| w.timer_comp1_load().set_bit()),
2 => systimer
.comp2_load
.write(|w| w.timer_comp2_load().set_bit()),
_ => unreachable!(),
}

systimer.conf.modify(|_r, w| match CHANNEL {
0 => w.target0_work_en().set_bit(),
1 => w.target1_work_en().set_bit(),
2 => w.target2_work_en().set_bit(),
_ => unreachable!(),
});
}

#[cfg(feature = "esp32s2")]
tconf.modify(|_r, w| match CHANNEL {
0 => w.target0_work_en().set_bit(),
1 => w.target0_work_en().set_bit(),
2 => w.target0_work_en().set_bit(),
_ => unreachable!(),
});
}
}
}
2 changes: 1 addition & 1 deletion esp32c3-hal/examples/blinky.rs
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ fn main() -> ! {

// Initialize the Delay peripheral, and use it to toggle the LED state in a
// loop.
let mut delay = Delay::new(peripherals.SYSTIMER, &clocks);
let mut delay = Delay::new(&clocks);

loop {
led.toggle().unwrap();
Expand Down
2 changes: 1 addition & 1 deletion esp32c3-hal/examples/gpio_interrupt.rs
Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ fn main() -> ! {
riscv::interrupt::enable();
}

let mut delay = Delay::new(peripherals.SYSTIMER, &clocks);
let mut delay = Delay::new(&clocks);
loop {
led.toggle().unwrap();
delay.delay_ms(500u32);
Expand Down
2 changes: 1 addition & 1 deletion esp32c3-hal/examples/hello_rgb.rs
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ fn main() -> ! {

// Initialize the Delay peripheral, and use it to toggle the LED state in a
// loop.
let mut delay = Delay::new(peripherals.SYSTIMER, &clocks);
let mut delay = Delay::new(&clocks);

let mut color = Hsv {
hue: 0,
Expand Down
2 changes: 1 addition & 1 deletion esp32c3-hal/examples/spi_loopback.rs
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ fn main() -> ! {
&clocks,
);

let mut delay = Delay::new(peripherals.SYSTIMER, &clocks);
let mut delay = Delay::new(&clocks);

loop {
let mut data = [0xde, 0xca, 0xfb, 0xad];
Expand Down
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