Housekeeping: CI and xtask updates

.github/actions/check/action.yml

@@ -39,7 +39,7 @@ runs:
 
     - name: Build (${{ inputs.package }})
       shell: bash
-      run: cd ${{ inputs.package }} && cargo check
+      run: cd ${{ inputs.package }} && cargo build
 
     # Install the MSRV of the specified toolchain:
 
@@ -64,9 +64,9 @@ runs:
     - name: Check MSRV
       if: startsWith(inputs.target, 'riscv')
       shell: bash
-      run: cd ${{ inputs.package }} && cargo +${{ inputs.msrv }} check
+      run: cd ${{ inputs.package }} && cargo +${{ inputs.msrv }} build
 
     - name: Check MSRV
       if: startsWith(inputs.target, 'xtensa')
       shell: bash
-      run: cd ${{ inputs.package }} && cargo check
+      run: cd ${{ inputs.package }} && cargo build

esp32/src/generic.rs

@@ -50,6 +50,8 @@ pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
     type Ux: Copy + PartialEq + From<Self>;
 }
+#[doc = " Marker for fields with fixed values"]
+pub trait IsEnum: FieldSpec {}
 #[doc = " Trait implemented by readable registers to enable the `read` method."]
 #[doc = ""]
 #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
@@ -340,15 +342,13 @@ impl<FI> BitReader<FI> {
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
-#[doc = " Write field Proxy with unsafe `bits`"]
-pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>;
-#[doc = " Write field Proxy with safe `bits`"]
-pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>;
-impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI>
+#[doc = " Write field Proxy"]
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+    raw::FieldWriter<'a, REG, WI, FI, Safety>;
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
-    REG::Ux: From<FI::Ux>,
 {
     #[doc = " Field width"]
     pub const WIDTH: u8 = WI;
@@ -362,6 +362,13 @@ where
     pub const fn offset(&self) -> u8 {
         self.o
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes raw bits to the field"]
     #[doc = ""]
     #[doc = " # Safety"]
@@ -373,41 +380,29 @@ where
         self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
         self.w
     }
-    #[doc = " Writes `variant` to the field"]
-    #[inline(always)]
-    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        unsafe { self.bits(FI::Ux::from(variant)) }
-    }
 }
-impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI>
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
     REG::Ux: From<FI::Ux>,
 {
-    #[doc = " Field width"]
-    pub const WIDTH: u8 = WI;
-    #[doc = " Field width"]
-    #[inline(always)]
-    pub const fn width(&self) -> u8 {
-        WI
-    }
-    #[doc = " Field offset"]
-    #[inline(always)]
-    pub const fn offset(&self) -> u8 {
-        self.o
-    }
     #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
-        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
-        self.w
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        unsafe { self.bits(value) }
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: IsEnum,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes `variant` to the field"]
     #[inline(always)]
     pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        self.bits(FI::Ux::from(variant))
+        unsafe { self.bits(FI::Ux::from(variant)) }
     }
 }
 macro_rules! bit_proxy {

esp32/src/lib.rs

@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.32.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.32.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]

esp32/src/rtc_cntl/clk_conf.rs

@@ -25,6 +25,7 @@ impl From<CK8M_DIV> for u8 {
 impl crate::FieldSpec for CK8M_DIV {
     type Ux = u8;
 }
+impl crate::IsEnum for CK8M_DIV {}
 #[doc = "Field `CK8M_DIV` reader - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024."]
 pub type CK8M_DIV_R = crate::FieldReader<CK8M_DIV>;
 impl CK8M_DIV_R {
@@ -61,7 +62,7 @@ impl CK8M_DIV_R {
     }
 }
 #[doc = "Field `CK8M_DIV` writer - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024."]
-pub type CK8M_DIV_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, CK8M_DIV>;
+pub type CK8M_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CK8M_DIV, crate::Safe>;
 impl<'a, REG> CK8M_DIV_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -209,6 +210,7 @@ impl From<SOC_CLK_SEL> for u8 {
 impl crate::FieldSpec for SOC_CLK_SEL {
     type Ux = u8;
 }
+impl crate::IsEnum for SOC_CLK_SEL {}
 #[doc = "Field `SOC_CLK_SEL` reader - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL"]
 pub type SOC_CLK_SEL_R = crate::FieldReader<SOC_CLK_SEL>;
 impl SOC_CLK_SEL_R {
@@ -245,7 +247,7 @@ impl SOC_CLK_SEL_R {
     }
 }
 #[doc = "Field `SOC_CLK_SEL` writer - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL"]
-pub type SOC_CLK_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, SOC_CLK_SEL>;
+pub type SOC_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SOC_CLK_SEL, crate::Safe>;
 impl<'a, REG> SOC_CLK_SEL_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -347,6 +349,7 @@ impl From<ANA_CLK_RTC_SEL> for u8 {
 impl crate::FieldSpec for ANA_CLK_RTC_SEL {
     type Ux = u8;
 }
+impl crate::IsEnum for ANA_CLK_RTC_SEL {}
 #[doc = "Field `ANA_CLK_RTC_SEL` reader - slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT"]
 pub type ANA_CLK_RTC_SEL_R = crate::FieldReader<ANA_CLK_RTC_SEL>;
 impl ANA_CLK_RTC_SEL_R {

esp32/src/timg0/wdtconfig0.rs

@@ -37,6 +37,7 @@ impl From<WDT_SYS_RESET_LENGTH> for u8 {
 impl crate::FieldSpec for WDT_SYS_RESET_LENGTH {
     type Ux = u8;
 }
+impl crate::IsEnum for WDT_SYS_RESET_LENGTH {}
 #[doc = "Field `WDT_SYS_RESET_LENGTH` reader - length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us"]
 pub type WDT_SYS_RESET_LENGTH_R = crate::FieldReader<WDT_SYS_RESET_LENGTH>;
 impl WDT_SYS_RESET_LENGTH_R {
@@ -97,7 +98,8 @@ impl WDT_SYS_RESET_LENGTH_R {
     }
 }
 #[doc = "Field `WDT_SYS_RESET_LENGTH` writer - length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us"]
-pub type WDT_SYS_RESET_LENGTH_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, WDT_SYS_RESET_LENGTH>;
+pub type WDT_SYS_RESET_LENGTH_W<'a, REG> =
+    crate::FieldWriter<'a, REG, 3, WDT_SYS_RESET_LENGTH, crate::Safe>;
 impl<'a, REG> WDT_SYS_RESET_LENGTH_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -175,6 +177,7 @@ impl From<WDT_CPU_RESET_LENGTH> for u8 {
 impl crate::FieldSpec for WDT_CPU_RESET_LENGTH {
     type Ux = u8;
 }
+impl crate::IsEnum for WDT_CPU_RESET_LENGTH {}
 #[doc = "Field `WDT_CPU_RESET_LENGTH` reader - length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us"]
 pub type WDT_CPU_RESET_LENGTH_R = crate::FieldReader<WDT_CPU_RESET_LENGTH>;
 impl WDT_CPU_RESET_LENGTH_R {
@@ -235,7 +238,8 @@ impl WDT_CPU_RESET_LENGTH_R {
     }
 }
 #[doc = "Field `WDT_CPU_RESET_LENGTH` writer - length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us"]
-pub type WDT_CPU_RESET_LENGTH_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, WDT_CPU_RESET_LENGTH>;
+pub type WDT_CPU_RESET_LENGTH_W<'a, REG> =
+    crate::FieldWriter<'a, REG, 3, WDT_CPU_RESET_LENGTH, crate::Safe>;
 impl<'a, REG> WDT_CPU_RESET_LENGTH_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,
@@ -313,6 +317,7 @@ impl From<WDT_STG3> for u8 {
 impl crate::FieldSpec for WDT_STG3 {
     type Ux = u8;
 }
+impl crate::IsEnum for WDT_STG3 {}
 #[doc = "Field `WDT_STG3` reader - Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system"]
 pub type WDT_STG3_R = crate::FieldReader<WDT_STG3>;
 impl WDT_STG3_R {
@@ -349,7 +354,7 @@ impl WDT_STG3_R {
     }
 }
 #[doc = "Field `WDT_STG3` writer - Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system"]
-pub type WDT_STG3_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, WDT_STG3>;
+pub type WDT_STG3_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WDT_STG3, crate::Safe>;
 impl<'a, REG> WDT_STG3_W<'a, REG>
 where
     REG: crate::Writable + crate::RegisterSpec,

esp32c2/src/generic.rs

@@ -50,6 +50,8 @@ pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
     type Ux: Copy + PartialEq + From<Self>;
 }
+#[doc = " Marker for fields with fixed values"]
+pub trait IsEnum: FieldSpec {}
 #[doc = " Trait implemented by readable registers to enable the `read` method."]
 #[doc = ""]
 #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
@@ -340,15 +342,13 @@ impl<FI> BitReader<FI> {
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
-#[doc = " Write field Proxy with unsafe `bits`"]
-pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>;
-#[doc = " Write field Proxy with safe `bits`"]
-pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>;
-impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI>
+#[doc = " Write field Proxy"]
+pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
+    raw::FieldWriter<'a, REG, WI, FI, Safety>;
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
-    REG::Ux: From<FI::Ux>,
 {
     #[doc = " Field width"]
     pub const WIDTH: u8 = WI;
@@ -362,6 +362,13 @@ where
     pub const fn offset(&self) -> u8 {
         self.o
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes raw bits to the field"]
     #[doc = ""]
     #[doc = " # Safety"]
@@ -373,41 +380,29 @@ where
         self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
         self.w
     }
-    #[doc = " Writes `variant` to the field"]
-    #[inline(always)]
-    pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        unsafe { self.bits(FI::Ux::from(variant)) }
-    }
 }
-impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI>
+impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
     REG::Ux: From<FI::Ux>,
 {
-    #[doc = " Field width"]
-    pub const WIDTH: u8 = WI;
-    #[doc = " Field width"]
-    #[inline(always)]
-    pub const fn width(&self) -> u8 {
-        WI
-    }
-    #[doc = " Field offset"]
-    #[inline(always)]
-    pub const fn offset(&self) -> u8 {
-        self.o
-    }
     #[doc = " Writes raw bits to the field"]
     #[inline(always)]
-    pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
-        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
-        self.w
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        unsafe { self.bits(value) }
     }
+}
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+where
+    REG: Writable + RegisterSpec,
+    FI: IsEnum,
+    REG::Ux: From<FI::Ux>,
+{
     #[doc = " Writes `variant` to the field"]
     #[inline(always)]
     pub fn variant(self, variant: FI) -> &'a mut W<REG> {
-        self.bits(FI::Ux::from(variant))
+        unsafe { self.bits(FI::Ux::from(variant)) }
     }
 }
 macro_rules! bit_proxy {

esp32c2/src/lib.rs

@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-C2 microcontrollers (generated using svd2rust v0.32.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.32.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-C2 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]