Skip to content
This repository was archived by the owner on Aug 9, 2022. It is now read-only.

Commit 1fdbcd6

Browse files
authored
Merge pull request #10 from jessebraham/examples
Add a basic example which blinks an LED
2 parents 7001818 + c54d6f0 commit 1fdbcd6

File tree

5 files changed

+137
-2
lines changed

5 files changed

+137
-2
lines changed

.cargo/config

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
[target.xtensa-esp32-none-elf]
2+
runner = "xtensa-esp32-elf-gdb -q -x xtensa.gdb"
3+
4+
[build]
5+
rustflags = [
6+
"-C", "link-arg=-nostartfiles",
7+
"-C", "link-arg=-Wl,-Tlink.x",
8+
]
9+
target = "xtensa-esp32-none-elf"

Cargo.toml

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,24 @@ version = "0.1.0"
44
authors = ["Scott Mabin <scott@mabez.dev>"]
55
edition = "2018"
66

7-
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
8-
97
[dependencies]
108
esp32 = { version = "0.2.2" }
119

1210
[dependencies.embedded-hal]
1311
features = ["unproven"]
1412
version = "0.2.3"
13+
14+
[dev-dependencies]
15+
panic-halt = "0.2.0"
16+
xtensa-lx6-rt = { git = "https://github.com/esp-rs/xtensa-lx6-rt", rev = "e5eb8c4cb893e47172e4e59eadd3d4d9c3093a06" }
17+
18+
[[example]]
19+
name = "blinky"
20+
21+
[profile.dev]
22+
incremental = false
23+
24+
[profile.release]
25+
lto = true
26+
incremental = false
27+
codegen-units = 1

build.rs

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
use std::env;
2+
use std::fs::File;
3+
use std::io::Write;
4+
use std::path::PathBuf;
5+
6+
fn main() {
7+
// Put the linker script somewhere the linker can find it
8+
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
9+
File::create(out.join("memory.x"))
10+
.unwrap()
11+
.write_all(include_bytes!("memory.x"))
12+
.unwrap();
13+
println!("cargo:rustc-link-search={}", out.display());
14+
15+
// Only re-run the build script when memory.x is changed,
16+
// instead of when any part of the source code changes.
17+
println!("cargo:rerun-if-changed=memory.x");
18+
}

examples/blinky.rs

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
#![no_std]
2+
#![no_main]
3+
4+
extern crate esp32_hal as hal;
5+
extern crate panic_halt;
6+
extern crate xtensa_lx6_rt;
7+
8+
use hal::prelude::*;
9+
use xtensa_lx6_rt::get_cycle_count;
10+
11+
/// The default clock source is the onboard crystal
12+
/// In most cases 40mhz (but can be as low as 2mhz depending on the board)
13+
const CORE_HZ: u32 = 40_000_000;
14+
15+
const WDT_WKEY_VALUE: u32 = 0x50D83AA1;
16+
17+
#[no_mangle]
18+
fn main() -> ! {
19+
let dp = unsafe { hal::pac::Peripherals::steal() };
20+
21+
let mut rtccntl = dp.RTCCNTL;
22+
let mut timg0 = dp.TIMG0;
23+
let mut timg1 = dp.TIMG1;
24+
25+
// (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431)
26+
// openocd disables the wdt's on halt
27+
// we will do it manually on startup
28+
disable_timg_wdts(&mut timg0, &mut timg1);
29+
disable_rtc_wdt(&mut rtccntl);
30+
31+
let pins = dp.GPIO.split();
32+
let mut led = pins.gpio2.into_open_drain_output();
33+
34+
loop {
35+
led.set_high().unwrap();
36+
delay(CORE_HZ);
37+
led.set_low().unwrap();
38+
delay(CORE_HZ);
39+
}
40+
}
41+
42+
fn disable_rtc_wdt(rtccntl: &mut hal::pac::RTCCNTL) {
43+
/* Disables the RTCWDT */
44+
rtccntl
45+
.wdtwprotect
46+
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
47+
rtccntl.wdtconfig0.modify(|_, w| unsafe {
48+
w.wdt_stg0()
49+
.bits(0x0)
50+
.wdt_stg1()
51+
.bits(0x0)
52+
.wdt_stg2()
53+
.bits(0x0)
54+
.wdt_stg3()
55+
.bits(0x0)
56+
.wdt_flashboot_mod_en()
57+
.clear_bit()
58+
.wdt_en()
59+
.clear_bit()
60+
});
61+
rtccntl.wdtwprotect.write(|w| unsafe { w.bits(0x0) });
62+
}
63+
64+
fn disable_timg_wdts(timg0: &mut hal::pac::TIMG0, timg1: &mut hal::pac::TIMG1) {
65+
timg0
66+
.wdtwprotect
67+
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
68+
timg1
69+
.wdtwprotect
70+
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
71+
72+
timg0.wdtconfig0.write(|w| unsafe { w.bits(0x0) });
73+
timg1.wdtconfig0.write(|w| unsafe { w.bits(0x0) });
74+
}
75+
76+
/// cycle accurate delay using the cycle counter register
77+
pub fn delay(clocks: u32) {
78+
// NOTE: does not account for rollover
79+
let target = get_cycle_count() + clocks;
80+
loop {
81+
if get_cycle_count() > target {
82+
break;
83+
}
84+
}
85+
}

memory.x

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/* Specify main memory areas */
2+
MEMORY
3+
{
4+
/* Use values from the ESP-IDF 'bootloader' component.
5+
/* TODO: Use human-readable lengths */
6+
/* TODO: Use the full memory map - this is just a test */
7+
/* vectors ( RX ) : ORIGIN = 0x40080000, len = 0x400 */
8+
iram_seg ( RX ) : ORIGIN = 0x40080400, len = 0xFC00
9+
dram_seg ( RW ) : ORIGIN = 0x3FFF0000, len = 0x1000
10+
}

0 commit comments

Comments
 (0)