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Merge pull request #10 from jessebraham/examples
Add a basic example which blinks an LED
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[target.xtensa-esp32-none-elf] | ||
runner = "xtensa-esp32-elf-gdb -q -x xtensa.gdb" | ||
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[build] | ||
rustflags = [ | ||
"-C", "link-arg=-nostartfiles", | ||
"-C", "link-arg=-Wl,-Tlink.x", | ||
] | ||
target = "xtensa-esp32-none-elf" |
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use std::env; | ||
use std::fs::File; | ||
use std::io::Write; | ||
use std::path::PathBuf; | ||
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fn main() { | ||
// Put the linker script somewhere the linker can find it | ||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); | ||
File::create(out.join("memory.x")) | ||
.unwrap() | ||
.write_all(include_bytes!("memory.x")) | ||
.unwrap(); | ||
println!("cargo:rustc-link-search={}", out.display()); | ||
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// Only re-run the build script when memory.x is changed, | ||
// instead of when any part of the source code changes. | ||
println!("cargo:rerun-if-changed=memory.x"); | ||
} |
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#![no_std] | ||
#![no_main] | ||
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extern crate esp32_hal as hal; | ||
extern crate panic_halt; | ||
extern crate xtensa_lx6_rt; | ||
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use hal::prelude::*; | ||
use xtensa_lx6_rt::get_cycle_count; | ||
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/// The default clock source is the onboard crystal | ||
/// In most cases 40mhz (but can be as low as 2mhz depending on the board) | ||
const CORE_HZ: u32 = 40_000_000; | ||
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const WDT_WKEY_VALUE: u32 = 0x50D83AA1; | ||
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#[no_mangle] | ||
fn main() -> ! { | ||
let dp = unsafe { hal::pac::Peripherals::steal() }; | ||
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let mut rtccntl = dp.RTCCNTL; | ||
let mut timg0 = dp.TIMG0; | ||
let mut timg1 = dp.TIMG1; | ||
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// (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431) | ||
// openocd disables the wdt's on halt | ||
// we will do it manually on startup | ||
disable_timg_wdts(&mut timg0, &mut timg1); | ||
disable_rtc_wdt(&mut rtccntl); | ||
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let pins = dp.GPIO.split(); | ||
let mut led = pins.gpio2.into_open_drain_output(); | ||
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loop { | ||
led.set_high().unwrap(); | ||
delay(CORE_HZ); | ||
led.set_low().unwrap(); | ||
delay(CORE_HZ); | ||
} | ||
} | ||
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fn disable_rtc_wdt(rtccntl: &mut hal::pac::RTCCNTL) { | ||
/* Disables the RTCWDT */ | ||
rtccntl | ||
.wdtwprotect | ||
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) }); | ||
rtccntl.wdtconfig0.modify(|_, w| unsafe { | ||
w.wdt_stg0() | ||
.bits(0x0) | ||
.wdt_stg1() | ||
.bits(0x0) | ||
.wdt_stg2() | ||
.bits(0x0) | ||
.wdt_stg3() | ||
.bits(0x0) | ||
.wdt_flashboot_mod_en() | ||
.clear_bit() | ||
.wdt_en() | ||
.clear_bit() | ||
}); | ||
rtccntl.wdtwprotect.write(|w| unsafe { w.bits(0x0) }); | ||
} | ||
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fn disable_timg_wdts(timg0: &mut hal::pac::TIMG0, timg1: &mut hal::pac::TIMG1) { | ||
timg0 | ||
.wdtwprotect | ||
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) }); | ||
timg1 | ||
.wdtwprotect | ||
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) }); | ||
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timg0.wdtconfig0.write(|w| unsafe { w.bits(0x0) }); | ||
timg1.wdtconfig0.write(|w| unsafe { w.bits(0x0) }); | ||
} | ||
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/// cycle accurate delay using the cycle counter register | ||
pub fn delay(clocks: u32) { | ||
// NOTE: does not account for rollover | ||
let target = get_cycle_count() + clocks; | ||
loop { | ||
if get_cycle_count() > target { | ||
break; | ||
} | ||
} | ||
} |
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/* Specify main memory areas */ | ||
MEMORY | ||
{ | ||
/* Use values from the ESP-IDF 'bootloader' component. | ||
/* TODO: Use human-readable lengths */ | ||
/* TODO: Use the full memory map - this is just a test */ | ||
/* vectors ( RX ) : ORIGIN = 0x40080000, len = 0x400 */ | ||
iram_seg ( RX ) : ORIGIN = 0x40080400, len = 0xFC00 | ||
dram_seg ( RW ) : ORIGIN = 0x3FFF0000, len = 0x1000 | ||
} |