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| 1 | +#![no_std] |
| 2 | +#![no_main] |
| 3 | + |
| 4 | +extern crate esp32_hal as hal; |
| 5 | +extern crate panic_halt; |
| 6 | +extern crate xtensa_lx6_rt; |
| 7 | + |
| 8 | +use hal::prelude::*; |
| 9 | +use xtensa_lx6_rt::get_cycle_count; |
| 10 | + |
| 11 | +/// The default clock source is the onboard crystal |
| 12 | +/// In most cases 40mhz (but can be as low as 2mhz depending on the board) |
| 13 | +const CORE_HZ: u32 = 40_000_000; |
| 14 | + |
| 15 | +const WDT_WKEY_VALUE: u32 = 0x50D83AA1; |
| 16 | + |
| 17 | +#[no_mangle] |
| 18 | +fn main() -> ! { |
| 19 | + let dp = unsafe { hal::pac::Peripherals::steal() }; |
| 20 | + |
| 21 | + let mut rtccntl = dp.RTCCNTL; |
| 22 | + let mut timg0 = dp.TIMG0; |
| 23 | + let mut timg1 = dp.TIMG1; |
| 24 | + |
| 25 | + // (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431) |
| 26 | + // openocd disables the wdt's on halt |
| 27 | + // we will do it manually on startup |
| 28 | + disable_timg_wdts(&mut timg0, &mut timg1); |
| 29 | + disable_rtc_wdt(&mut rtccntl); |
| 30 | + |
| 31 | + let pins = dp.GPIO.split(); |
| 32 | + let mut led = pins.gpio2.into_open_drain_output(); |
| 33 | + |
| 34 | + loop { |
| 35 | + led.set_high().unwrap(); |
| 36 | + delay(CORE_HZ); |
| 37 | + led.set_low().unwrap(); |
| 38 | + delay(CORE_HZ); |
| 39 | + } |
| 40 | +} |
| 41 | + |
| 42 | +fn disable_rtc_wdt(rtccntl: &mut hal::pac::RTCCNTL) { |
| 43 | + /* Disables the RTCWDT */ |
| 44 | + rtccntl |
| 45 | + .wdtwprotect |
| 46 | + .write(|w| unsafe { w.bits(WDT_WKEY_VALUE) }); |
| 47 | + rtccntl.wdtconfig0.modify(|_, w| unsafe { |
| 48 | + w.wdt_stg0() |
| 49 | + .bits(0x0) |
| 50 | + .wdt_stg1() |
| 51 | + .bits(0x0) |
| 52 | + .wdt_stg2() |
| 53 | + .bits(0x0) |
| 54 | + .wdt_stg3() |
| 55 | + .bits(0x0) |
| 56 | + .wdt_flashboot_mod_en() |
| 57 | + .clear_bit() |
| 58 | + .wdt_en() |
| 59 | + .clear_bit() |
| 60 | + }); |
| 61 | + rtccntl.wdtwprotect.write(|w| unsafe { w.bits(0x0) }); |
| 62 | +} |
| 63 | + |
| 64 | +fn disable_timg_wdts(timg0: &mut hal::pac::TIMG0, timg1: &mut hal::pac::TIMG1) { |
| 65 | + timg0 |
| 66 | + .wdtwprotect |
| 67 | + .write(|w| unsafe { w.bits(WDT_WKEY_VALUE) }); |
| 68 | + timg1 |
| 69 | + .wdtwprotect |
| 70 | + .write(|w| unsafe { w.bits(WDT_WKEY_VALUE) }); |
| 71 | + |
| 72 | + timg0.wdtconfig0.write(|w| unsafe { w.bits(0x0) }); |
| 73 | + timg1.wdtconfig0.write(|w| unsafe { w.bits(0x0) }); |
| 74 | +} |
| 75 | + |
| 76 | +/// cycle accurate delay using the cycle counter register |
| 77 | +pub fn delay(clocks: u32) { |
| 78 | + // NOTE: does not account for rollover |
| 79 | + let target = get_cycle_count() + clocks; |
| 80 | + loop { |
| 81 | + if get_cycle_count() > target { |
| 82 | + break; |
| 83 | + } |
| 84 | + } |
| 85 | +} |
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