Add a basic example which blinks an LED

.cargo/config

@@ -0,0 +1,10 @@
+[target.xtensa-esp32-none-elf]
+runner = "xtensa-esp32-elf-gdb -q -x xtensa.gdb"
+
+[build]
+rustflags = [
+  "-C", "link-arg=-nostartfiles",
+  "-C", "debuginfo=0", # not 2
+  "-C", "link-arg=-Wl,-Tlink.x",
+]
+target = "xtensa-esp32-none-elf"

Cargo.toml

@@ -12,3 +12,22 @@ esp32 = { version = "0.2.2" }
 [dependencies.embedded-hal]
 features = ["unproven"]
 version = "0.2.3"
+
+[dev-dependencies]
+panic-halt = "0.2.0"
+xtensa-lx6-rt = { git = "https://github.com/esp-rs/xtensa-lx6-rt", rev = "89cea20c441d4a1624de99c7278df13af5c211a4" }
+
+[[example]]
+name = "blinky"
+
+[profile.dev]
+lto = true 
+incremental = false
+debug = false # debug adds frame pointers - which must be omitted
+codegen-units = 1
+
+[profile.release]
+lto = true
+incremental = false
+debug = false # debug adds frame pointers - which must be omitted
+codegen-units = 1

build.rs

@@ -0,0 +1,18 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when memory.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=memory.x");
+}

examples/blinky.rs

@@ -0,0 +1,94 @@
+#![no_std]
+#![no_main]
+#![feature(asm)]
+
+extern crate esp32_hal as hal;
+extern crate panic_halt;
+extern crate xtensa_lx6_rt;
+
+use hal::prelude::*;
+
+/// The default clock source is the onboard crystal
+/// In most cases 40mhz (but can be as low as 2mhz depending on the board)
+const CORE_HZ: u32 = 40_000_000;
+
+const WDT_WKEY_VALUE: u32 = 0x50D83AA1;
+
+#[no_mangle]
+fn main() -> ! {
+    let dp = unsafe { hal::pac::Peripherals::steal() };
+
+    let mut rtccntl = dp.RTCCNTL;
+    let mut timg0 = dp.TIMG0;
+    let mut timg1 = dp.TIMG1;
+
+    // (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431)
+    // openocd disables the wdt's on halt
+    // we will do it manually on startup
+    disable_timg_wdts(&mut timg0, &mut timg1);
+    disable_rtc_wdt(&mut rtccntl);
+
+    let pins = dp.GPIO.split();
+    let mut led = pins.gpio2.into_open_drain_output();
+
+    loop {
+        led.set_high().unwrap();
+        delay(CORE_HZ);
+        led.set_low().unwrap();
+        delay(CORE_HZ);
+    }
+}
+
+fn disable_rtc_wdt(rtccntl: &mut hal::pac::RTCCNTL) {
+    /* Disables the RTCWDT */
+    rtccntl
+        .wdtwprotect
+        .write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
+    rtccntl.wdtconfig0.modify(|_, w| unsafe {
+        w.wdt_stg0()
+            .bits(0x0)
+            .wdt_stg1()
+            .bits(0x0)
+            .wdt_stg2()
+            .bits(0x0)
+            .wdt_stg3()
+            .bits(0x0)
+            .wdt_flashboot_mod_en()
+            .clear_bit()
+            .wdt_en()
+            .clear_bit()
+    });
+    rtccntl.wdtwprotect.write(|w| unsafe { w.bits(0x0) });
+}
+
+fn disable_timg_wdts(timg0: &mut hal::pac::TIMG0, timg1: &mut hal::pac::TIMG1) {
+    timg0
+        .wdtwprotect
+        .write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
+    timg1
+        .wdtwprotect
+        .write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
+
+    timg0.wdtconfig0.write(|w| unsafe { w.bits(0x0) });
+    timg1.wdtconfig0.write(|w| unsafe { w.bits(0x0) });
+}
+
+/// cycle accurate delay using the cycle counter register
+pub fn delay(clocks: u32) {
+    // NOTE: does not account for rollover
+    let target = get_ccount() + clocks;
+    loop {
+        if get_ccount() > target {
+            break;
+        }
+    }
+}
+
+/// Performs a special register read to read the current cycle count.
+/// In the future, this can be precompiled to a archive (.a) and linked to so we don't
+/// have to require the asm nightly feature - see cortex-m-rt for more details
+pub fn get_ccount() -> u32 {
+    let x: u32;
+    unsafe { asm!("rsr.ccount a2" : "={a2}"(x) ) };
+    x
+}

memory.x

@@ -0,0 +1,10 @@
+/* Specify main memory areas */
+MEMORY
+{
+  /* Use values from the ESP-IDF 'bootloader' component.
+  /* TODO: Use human-readable lengths */
+  /* TODO: Use the full memory map - this is just a test */
+  /* vectors ( RX )       : ORIGIN = 0x40080000, len = 0x400 */
+  iram_seg ( RX )       : ORIGIN = 0x40080400, len = 0xFC00
+  dram_seg ( RW )       : ORIGIN = 0x3FFF0000, len = 0x1000
+}