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asm! support the the Xtensa architecture
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@MabezDev
MabezDev committed Aug 12, 2021
1 parent 8fc1989 commit 93ee290
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Showing 7 changed files with 514 additions and 1 deletion.
8 changes: 8 additions & 0 deletions compiler/rustc_codegen_llvm/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -288,6 +288,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
InlineAsmArch::SpirV => {}
InlineAsmArch::Wasm32 => {}
InlineAsmArch::Xtensa => {}
InlineAsmArch::Bpf => {}
}
}
Expand Down Expand Up @@ -594,6 +595,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => "b",
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
Expand Down Expand Up @@ -637,6 +641,7 @@ fn modifier_to_llvm(
InlineAsmRegClass::Mips(_) => None,
InlineAsmRegClass::Nvptx(_) => None,
InlineAsmRegClass::PowerPC(_) => None,
InlineAsmRegClass::Xtensa(_) => None,
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
Expand Down Expand Up @@ -712,6 +717,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => cx.type_i1(),
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
Expand Down
30 changes: 30 additions & 0 deletions compiler/rustc_codegen_ssa/src/target_features.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -210,6 +210,34 @@ const WASM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("nontrapping-fptoint", Some(sym::wasm_target_feature)),
];

const XTENSA_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("fp", Some(sym::xtensa_target_feature)),
("windowed", Some(sym::xtensa_target_feature)),
("bool", Some(sym::xtensa_target_feature)),
("loop", Some(sym::xtensa_target_feature)),
("sext", Some(sym::xtensa_target_feature)),
("nsa", Some(sym::xtensa_target_feature)),
("mul32", Some(sym::xtensa_target_feature)),
("mul32high", Some(sym::xtensa_target_feature)),
("div32", Some(sym::xtensa_target_feature)),
("mac16", Some(sym::xtensa_target_feature)),
("dfpaccel", Some(sym::xtensa_target_feature)),
("s32c1i", Some(sym::xtensa_target_feature)),
("threadptr", Some(sym::xtensa_target_feature)),
("extendedl32r", Some(sym::xtensa_target_feature)),
("atomctl", Some(sym::xtensa_target_feature)),
("memctl", Some(sym::xtensa_target_feature)),
("debug", Some(sym::xtensa_target_feature)),
("exception", Some(sym::xtensa_target_feature)),
("coprocessor", Some(sym::xtensa_target_feature)),
("interrupt", Some(sym::xtensa_target_feature)),
("rvector", Some(sym::xtensa_target_feature)),
("timerint", Some(sym::xtensa_target_feature)),
("prid", Some(sym::xtensa_target_feature)),
("regprotect", Some(sym::xtensa_target_feature)),
("miscsr", Some(sym::xtensa_target_feature)),
];

const BPF_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[("alu32", Some(sym::bpf_target_feature))];

/// When rustdoc is running, provide a list of all known features so that all their respective
Expand All @@ -226,6 +254,7 @@ pub fn all_known_features() -> impl Iterator<Item = (&'static str, Option<Symbol
.chain(MIPS_ALLOWED_FEATURES.iter())
.chain(RISCV_ALLOWED_FEATURES.iter())
.chain(WASM_ALLOWED_FEATURES.iter())
.chain(XTENSA_ALLOWED_FEATURES.iter())
.chain(BPF_ALLOWED_FEATURES.iter())
.cloned()
}
Expand All @@ -240,6 +269,7 @@ pub fn supported_target_features(sess: &Session) -> &'static [(&'static str, Opt
"powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES,
"riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES,
"wasm32" | "wasm64" => WASM_ALLOWED_FEATURES,
"xtensa" => XTENSA_ALLOWED_FEATURES,
"bpf" => BPF_ALLOWED_FEATURES,
_ => &[],
}
Expand Down
2 changes: 2 additions & 0 deletions compiler/rustc_span/src/symbol.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -332,6 +332,7 @@ symbols! {
braced_empty_structs,
branch,
breakpoint,
breg,
bridge,
bswap,
c_str,
Expand Down Expand Up @@ -1336,6 +1337,7 @@ symbols! {
wreg,
write_bytes,
xmm_reg,
xtensa_target_feature,
ymm_reg,
zmm_reg,
}
Expand Down
28 changes: 28 additions & 0 deletions compiler/rustc_target/src/asm/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -157,6 +157,7 @@ mod riscv;
mod spirv;
mod wasm;
mod x86;
mod xtensa;

pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
Expand All @@ -168,6 +169,7 @@ pub use powerpc::{PowerPCInlineAsmReg, PowerPCInlineAsmRegClass};
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
pub use xtensa::{XtensaInlineAsmReg, XtensaInlineAsmRegClass};
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};

#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
Expand All @@ -186,6 +188,7 @@ pub enum InlineAsmArch {
PowerPC64,
SpirV,
Wasm32,
Xtensa,
Bpf,
}

Expand All @@ -208,6 +211,7 @@ impl FromStr for InlineAsmArch {
"mips64" => Ok(Self::Mips64),
"spirv" => Ok(Self::SpirV),
"wasm32" => Ok(Self::Wasm32),
"xtensa" => Ok(Self::Xtensa),
"bpf" => Ok(Self::Bpf),
_ => Err(()),
}
Expand Down Expand Up @@ -237,6 +241,7 @@ pub enum InlineAsmReg {
Mips(MipsInlineAsmReg),
SpirV(SpirVInlineAsmReg),
Wasm(WasmInlineAsmReg),
Xtensa(XtensaInlineAsmReg),
Bpf(BpfInlineAsmReg),
// Placeholder for invalid register constraints for the current target
Err,
Expand All @@ -252,6 +257,7 @@ impl InlineAsmReg {
Self::PowerPC(r) => r.name(),
Self::Hexagon(r) => r.name(),
Self::Mips(r) => r.name(),
Self::Xtensa(r) => r.name(),
Self::Bpf(r) => r.name(),
Self::Err => "<reg>",
}
Expand All @@ -266,6 +272,7 @@ impl InlineAsmReg {
Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),
Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
Self::Xtensa(r) => InlineAsmRegClass::Xtensa(r.reg_class()),
Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
Self::Err => InlineAsmRegClass::Err,
}
Expand Down Expand Up @@ -311,6 +318,9 @@ impl InlineAsmReg {
InlineAsmArch::Wasm32 => {
Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
InlineAsmArch::Xtensa => {
Self::Xtensa(XtensaInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
InlineAsmArch::Bpf => {
Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
Expand All @@ -333,6 +343,7 @@ impl InlineAsmReg {
Self::PowerPC(r) => r.emit(out, arch, modifier),
Self::Hexagon(r) => r.emit(out, arch, modifier),
Self::Mips(r) => r.emit(out, arch, modifier),
Self::Xtensa(r) => r.emit(out, arch, modifier),
Self::Bpf(r) => r.emit(out, arch, modifier),
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
}
Expand All @@ -347,6 +358,7 @@ impl InlineAsmReg {
Self::PowerPC(_) => cb(self),
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
Self::Mips(_) => cb(self),
Self::Xtensa(_) => cb(self),
Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
}
Expand Down Expand Up @@ -376,6 +388,7 @@ pub enum InlineAsmRegClass {
Mips(MipsInlineAsmRegClass),
SpirV(SpirVInlineAsmRegClass),
Wasm(WasmInlineAsmRegClass),
Xtensa(XtensaInlineAsmRegClass),
Bpf(BpfInlineAsmRegClass),
// Placeholder for invalid register constraints for the current target
Err,
Expand All @@ -394,6 +407,7 @@ impl InlineAsmRegClass {
Self::Mips(r) => r.name(),
Self::SpirV(r) => r.name(),
Self::Wasm(r) => r.name(),
Self::Xtensa(r) => r.name(),
Self::Bpf(r) => r.name(),
Self::Err => rustc_span::symbol::sym::reg,
}
Expand All @@ -414,6 +428,7 @@ impl InlineAsmRegClass {
Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
Self::Xtensa(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Xtensa),
Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
Expand Down Expand Up @@ -441,6 +456,7 @@ impl InlineAsmRegClass {
Self::Mips(r) => r.suggest_modifier(arch, ty),
Self::SpirV(r) => r.suggest_modifier(arch, ty),
Self::Wasm(r) => r.suggest_modifier(arch, ty),
Self::Xtensa(r) => r.suggest_modifier(arch, ty),
Self::Bpf(r) => r.suggest_modifier(arch, ty),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
Expand All @@ -464,6 +480,7 @@ impl InlineAsmRegClass {
Self::Mips(r) => r.default_modifier(arch),
Self::SpirV(r) => r.default_modifier(arch),
Self::Wasm(r) => r.default_modifier(arch),
Self::Xtensa(r) => r.default_modifier(arch),
Self::Bpf(r) => r.default_modifier(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
Expand All @@ -486,6 +503,7 @@ impl InlineAsmRegClass {
Self::Mips(r) => r.supported_types(arch),
Self::SpirV(r) => r.supported_types(arch),
Self::Wasm(r) => r.supported_types(arch),
Self::Xtensa(r) => r.supported_types(arch),
Self::Bpf(r) => r.supported_types(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
Expand All @@ -511,6 +529,7 @@ impl InlineAsmRegClass {
}
InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::Xtensa => Self::Xtensa(XtensaInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
})
}
Expand All @@ -529,6 +548,7 @@ impl InlineAsmRegClass {
Self::Mips(r) => r.valid_modifiers(arch),
Self::SpirV(r) => r.valid_modifiers(arch),
Self::Wasm(r) => r.valid_modifiers(arch),
Self::Xtensa(r) => r.valid_modifiers(arch),
Self::Bpf(r) => r.valid_modifiers(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
Expand Down Expand Up @@ -573,6 +593,7 @@ impl fmt::Display for InlineAsmRegOrRegClass {
/// Set of types which can be used with a particular register class.
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
pub enum InlineAsmType {
I1,
I8,
I16,
I32,
Expand All @@ -596,6 +617,7 @@ impl InlineAsmType {

pub fn size(self) -> Size {
Size::from_bytes(match self {
Self::I1 => return Size::from_bits(1),
Self::I8 => 1,
Self::I16 => 2,
Self::I32 => 4,
Expand All @@ -617,6 +639,7 @@ impl InlineAsmType {
impl fmt::Display for InlineAsmType {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
match *self {
Self::I1 => f.write_str("i1"),
Self::I8 => f.write_str("i8"),
Self::I16 => f.write_str("i16"),
Self::I32 => f.write_str("i32"),
Expand Down Expand Up @@ -699,6 +722,11 @@ pub fn allocatable_registers(
wasm::fill_reg_map(arch, has_feature, target, &mut map);
map
}
InlineAsmArch::Xtensa => {
let mut map = xtensa::regclass_map();
xtensa::fill_reg_map(arch, has_feature, target, &mut map);
map
}
InlineAsmArch::Bpf => {
let mut map = bpf::regclass_map();
bpf::fill_reg_map(arch, has_feature, target, &mut map);
Expand Down
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