Allow setting alternate TX for UART 0, so GPIO1 is available as SPI_CS1#1424
Merged
igrr merged 3 commits intoesp8266:masterfrom Jan 18, 2016
Merged
Allow setting alternate TX for UART 0, so GPIO1 is available as SPI_CS1#1424igrr merged 3 commits intoesp8266:masterfrom
igrr merged 3 commits intoesp8266:masterfrom