Feature/esp32h2 support

.github/scripts/on-push.sh

@@ -69,6 +69,7 @@ if [ "$BUILD_PIO" -eq 0 ]; then
  FQBN_ESP32S3="espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=huge_app"
  FQBN_ESP32C3="espressif:esp32:esp32c3:PartitionScheme=huge_app"
  FQBN_ESP32C6="espressif:esp32:esp32c6:PartitionScheme=huge_app"
+ FQBN_ESP32H2="espressif:esp32:esp32h2:PartitionScheme=huge_app"
 
  SKETCHES_ESP32="\
  $ARDUINO_ESP32_PATH/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino\
@@ -87,6 +88,7 @@ if [ "$BUILD_PIO" -eq 0 ]; then
  build "esp32s2" $FQBN_ESP32S2 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32XX
  build "esp32c3" $FQBN_ESP32C3 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32XX
  build "esp32c6" $FQBN_ESP32C6 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32XX
+ build "esp32h2" $FQBN_ESP32H2 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32XX
  build "esp32" $FQBN_ESP32 $CHUNK_INDEX $CHUNKS_CNT $SKETCHES_ESP32
 else
  source ${SCRIPTS_DIR}/install-platformio-esp32.sh

.github/scripts/sketch_utils.sh

@@ -75,6 +75,7 @@ function build_sketch(){ # build_sketch <ide_path> <user_path> <path-to-ino> [ex
  esp32s3_opts="PSRAM=opi,USBMode=default,PartitionScheme=huge_app"
  esp32c3_opts="PartitionScheme=huge_app"
  esp32c6_opts="PartitionScheme=huge_app"
+ esp32h2_opts="PartitionScheme=huge_app"
 
  # Select the common part of the FQBN based on the target. The rest will be
  # appended depending on the passed options.
@@ -95,6 +96,9 @@ function build_sketch(){ # build_sketch <ide_path> <user_path> <path-to-ino> [ex
  "esp32c6")
  fqbn="espressif:esp32:esp32c6:${options:-$esp32c6_opts}"
  ;;
+ "esp32h2")
+ fqbn="espressif:esp32:esp32h2:${options:-$esp32h2_opts}"
+ ;;
  esac
 
  # Make it look like a JSON array.

.github/workflows/hil.yml

@@ -47,7 +47,7 @@ jobs:
  runs-on: ubuntu-latest
  strategy:
  matrix:
- chip: ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6']
+ chip: ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2']
  chunks: ${{fromJson(needs.gen_chunks.outputs.chunks)}}
  steps:
  - name: Checkout Repository
@@ -76,7 +76,7 @@ jobs:
  strategy:
  fail-fast: false
  matrix:
- chip: ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6']
+ chip: ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c6', 'esp32h2']
  chunks: ${{fromJson(needs.gen_chunks.outputs.chunks)}}
  container:
  image: python:3.10.1-bullseye

.github/workflows/lib.yml

@@ -37,6 +37,7 @@ jobs:
  - esp32c3
  - esp32s3
  - esp32c6
+ - esp32h2
 
  include:
  - target: esp32
@@ -49,6 +50,8 @@ jobs:
  fqbn: espressif:esp32:esp32s3
  - target: esp32c6
  fqbn: espressif:esp32:esp32c6
+ - target: esp32h2
+ fqbn: espressif:esp32:esp32h2
 
 
  steps:

boards.txt

@@ -29,6 +29,163 @@ menu.LORAWAN_PREAMBLE_LENGTH=LoRaWan Preamble Length
 ### DO NOT PUT BOARDS ABOVE THE OFFICIAL ESPRESSIF BOARDS! ###
 ##############################################################
 
+esp32h2.name=ESP32H2 Dev Module
+esp32h2.vid.0=0x303a
+esp32h2.pid.0=0x1001
+
+esp32h2.bootloader.tool=esptool_py
+esp32h2.bootloader.tool.default=esptool_py
+
+esp32h2.upload.tool=esptool_py
+esp32h2.upload.tool.default=esptool_py
+esp32h2.upload.tool.network=esp_ota
+
+esp32h2.upload.maximum_size=1310720
+esp32h2.upload.maximum_data_size=327680
+esp32h2.upload.flags=
+esp32h2.upload.extra_flags=
+esp32h2.upload.use_1200bps_touch=false
+esp32h2.upload.wait_for_upload_port=false
+
+esp32h2.serial.disableDTR=false
+esp32h2.serial.disableRTS=false
+
+esp32h2.build.tarch=riscv32
+esp32h2.build.target=esp
+esp32h2.build.mcu=esp32h2
+esp32h2.build.core=esp32
+esp32h2.build.variant=esp32h2
+esp32h2.build.board=ESP32H2_DEV
+esp32h2.build.bootloader_addr=0x0
+
+esp32h2.build.cdc_on_boot=0
+esp32h2.build.f_cpu=96000000L
+esp32h2.build.flash_size=4MB
+esp32h2.build.flash_freq=64m
+esp32h2.build.img_freq=48m
+esp32h2.build.flash_mode=qio
+esp32h2.build.boot=qio
+esp32h2.build.partitions=default
+esp32h2.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32h2.menu.JTAGAdapter.default=Disabled
+esp32h2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32h2.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32h2.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg
+esp32h2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32h2.menu.JTAGAdapter.external=FTDI Adapter
+esp32h2.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg
+esp32h2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32h2.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32h2.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg
+esp32h2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32h2.menu.CDCOnBoot.default=Disabled
+esp32h2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32h2.menu.CDCOnBoot.cdc=Enabled
+esp32h2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32h2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32h2.menu.PartitionScheme.default.build.partitions=default
+esp32h2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32h2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32h2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32h2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32h2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32h2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32h2.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32h2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32h2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32h2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32h2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32h2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32h2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32h2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32h2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32h2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32h2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32h2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32h2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32h2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32h2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32h2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32h2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32h2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32h2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32h2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32h2.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32h2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32h2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32h2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32h2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32h2.menu.PartitionScheme.rainmaker=RainMaker
+esp32h2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32h2.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728
+
+esp32h2.menu.FlashMode.qio=QIO
+esp32h2.menu.FlashMode.qio.build.flash_mode=dio
+esp32h2.menu.FlashMode.qio.build.boot=qio
+esp32h2.menu.FlashMode.dio=DIO
+esp32h2.menu.FlashMode.dio.build.flash_mode=dio
+esp32h2.menu.FlashMode.dio.build.boot=dio
+
+esp32h2.menu.FlashFreq.64=64MHz
+esp32h2.menu.FlashFreq.64.build.flash_freq=64m
+esp32h2.menu.FlashFreq.64.build.img_freq=48m
+#esp32h2.menu.FlashFreq.32=32MHz
+#esp32h2.menu.FlashFreq.32.build.flash_freq=32m
+#esp32h2.menu.FlashFreq.32.build.img_freq=24m
+esp32h2.menu.FlashFreq.16=16MHz
+esp32h2.menu.FlashFreq.16.build.flash_freq=16m
+esp32h2.menu.FlashFreq.16.build.img_freq=12m
+
+esp32h2.menu.FlashSize.4M=4MB (32Mb)
+esp32h2.menu.FlashSize.4M.build.flash_size=4MB
+esp32h2.menu.FlashSize.8M=8MB (64Mb)
+esp32h2.menu.FlashSize.8M.build.flash_size=8MB
+esp32h2.menu.FlashSize.8M.build.partitions=default_8MB
+esp32h2.menu.FlashSize.2M=2MB (16Mb)
+esp32h2.menu.FlashSize.2M.build.flash_size=2MB
+esp32h2.menu.FlashSize.2M.build.partitions=minimal
+esp32h2.menu.FlashSize.16M=16MB (128Mb)
+esp32h2.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32h2.menu.UploadSpeed.921600=921600
+esp32h2.menu.UploadSpeed.921600.upload.speed=921600
+esp32h2.menu.UploadSpeed.115200=115200
+esp32h2.menu.UploadSpeed.115200.upload.speed=115200
+esp32h2.menu.UploadSpeed.256000.windows=256000
+esp32h2.menu.UploadSpeed.256000.upload.speed=256000
+esp32h2.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32h2.menu.UploadSpeed.230400=230400
+esp32h2.menu.UploadSpeed.230400.upload.speed=230400
+esp32h2.menu.UploadSpeed.460800.linux=460800
+esp32h2.menu.UploadSpeed.460800.macosx=460800
+esp32h2.menu.UploadSpeed.460800.upload.speed=460800
+esp32h2.menu.UploadSpeed.512000.windows=512000
+esp32h2.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32h2.menu.DebugLevel.none=None
+esp32h2.menu.DebugLevel.none.build.code_debug=0
+esp32h2.menu.DebugLevel.error=Error
+esp32h2.menu.DebugLevel.error.build.code_debug=1
+esp32h2.menu.DebugLevel.warn=Warn
+esp32h2.menu.DebugLevel.warn.build.code_debug=2
+esp32h2.menu.DebugLevel.info=Info
+esp32h2.menu.DebugLevel.info.build.code_debug=3
+esp32h2.menu.DebugLevel.debug=Debug
+esp32h2.menu.DebugLevel.debug.build.code_debug=4
+esp32h2.menu.DebugLevel.verbose=Verbose
+esp32h2.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32h2.menu.EraseFlash.none=Disabled
+esp32h2.menu.EraseFlash.none.upload.erase_cmd=
+esp32h2.menu.EraseFlash.all=Enabled
+esp32h2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
 esp32c6.name=ESP32C6 Dev Module
 esp32c6.vid.0=0x303a
 esp32c6.pid.0=0x1001

cores/esp32/Esp.cpp

@@ -54,6 +54,9 @@ extern "C" {
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/spi_flash.h"
 #define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c6 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32h2 is located at 0x0000
 #else 
 #error Target CONFIG_IDF_TARGET is not supported
 #endif
@@ -363,8 +366,12 @@ FlashMode_t EspClass::getFlashChipMode(void)
  #if CONFIG_IDF_TARGET_ESP32S2
  uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL);
  #else
+ #if CONFIG_IDF_TARGET_ESP32H2
+ uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8);
+ #else
  uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
  #endif
+ #endif
  /* Not all of the following constants are already defined in older versions of spi_reg.h, so do it manually for now*/
  if (spi_ctrl & BIT(24)) { //SPI_FREAD_QIO
  return (FM_QIO);

cores/esp32/HardwareSerial.cpp

@@ -30,6 +30,8 @@
 #define SOC_RX0 20
 #elif CONFIG_IDF_TARGET_ESP32C6
 #define SOC_RX0 17
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define SOC_RX0 23
 #endif
 #endif
 
@@ -42,6 +44,8 @@
 #define SOC_TX0 21
 #elif CONFIG_IDF_TARGET_ESP32C6
 #define SOC_TX0 16
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define SOC_TX0 24
 #endif
 #endif
 
@@ -61,6 +65,8 @@ void serialEvent(void) {}
 #define RX1 15
 #elif CONFIG_IDF_TARGET_ESP32C6
 #define RX1 5
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define RX1 0
 #endif
 #endif
 
@@ -73,8 +79,10 @@ void serialEvent(void) {}
 #define TX1 19
 #elif CONFIG_IDF_TARGET_ESP32S3
 #define TX1 16
-#elif CONFIG_IDF_TARGET_ESP32C6
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
 #define TX1 4
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define TX1 1
 #endif
 #endif
 

cores/esp32/esp32-hal-adc.c

@@ -91,7 +91,7 @@ esp_err_t __analogChannelConfig(adc_bitwidth_t width, adc_attenuation_t atten, i
  log_e("adc_cali_create_scheme_curve_fitting failed with error: %d", err);
  return err;
  }
- #elif !defined(CONFIG_IDF_TARGET_ESP32C6) //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+ #elif !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
  log_d("Deleting ADC_UNIT_%d line cali handle",adc_unit);
  err = adc_cali_delete_scheme_line_fitting(adc_cali_handle[adc_unit]);
  if(err != ESP_OK){
@@ -278,7 +278,7 @@ uint32_t __analogReadMilliVolts(uint8_t pin){
  .bitwidth = __analogWidth,
  };
  err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_cali_handle[adc_unit]);
- #elif !defined(CONFIG_IDF_TARGET_ESP32C6) //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+ #elif !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
  adc_cali_line_fitting_config_t cali_config = {
  .unit_id = adc_unit,
  .bitwidth = __analogWidth,

cores/esp32/esp32-hal-cpu.c

@@ -19,7 +19,7 @@
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "soc/rtc.h"
-#ifndef CONFIG_IDF_TARGET_ESP32C6
+#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
 #include "soc/rtc_cntl_reg.h"
 #include "soc/apb_ctrl_reg.h"
 #endif
@@ -42,6 +42,8 @@
 #include "esp32c3/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
 #else 
 #error Target CONFIG_IDF_TARGET is not supported
 #endif
@@ -151,7 +153,7 @@ bool removeApbChangeCallback(void * arg, apb_change_cb_t cb){
 }
 
 static uint32_t calculateApb(rtc_cpu_freq_config_t * conf){
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
  return APB_CLK_FREQ;
 #else
  if(conf->freq_mhz >= 80){
@@ -167,7 +169,9 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
  rtc_cpu_freq_config_t conf, cconf;
  uint32_t capb, apb;
  //Get XTAL Frequency and calculate min CPU MHz
+#ifndef CONFIG_IDF_TARGET_ESP32H2
  rtc_xtal_freq_t xtal = rtc_clk_xtal_freq_get();
+#endif
 #if CONFIG_IDF_TARGET_ESP32
  if(xtal > RTC_XTAL_FREQ_AUTO){
  if(xtal < RTC_XTAL_FREQ_40M) {
@@ -181,6 +185,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
  }
  }
 #endif
+#ifndef CONFIG_IDF_TARGET_ESP32H2
  if(cpu_freq_mhz > xtal && cpu_freq_mhz != 240 && cpu_freq_mhz != 160 && cpu_freq_mhz != 80){
  if(xtal >= RTC_XTAL_FREQ_40M){
  log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal/2, xtal/4);
@@ -189,6 +194,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
  }
  return false;
  }
+#endif
 #if CONFIG_IDF_TARGET_ESP32
  //check if cpu supports the frequency
  if(cpu_freq_mhz == 240){
@@ -222,7 +228,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
  }
  //Make the frequency change
  rtc_clk_cpu_freq_set_config_fast(&conf);
-#ifndef CONFIG_IDF_TARGET_ESP32C6
+#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
  if(capb != apb){
  //Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
  //if(conf.freq_mhz < 80){
@@ -235,7 +241,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
  }
 #endif
  //Update FreeRTOS Tick Divisor
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
 
 #elif CONFIG_IDF_TARGET_ESP32S3