esp32ulp: fix periph.reg.address range for esp32s2. Add esp32s3 mcpu

Closes #3
espressif · Dec 19, 2023 · 94ef82c · 94ef82c
1 parent 154d59d
commit 94ef82c
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Showing 4 changed files with 32 additions and 13 deletions.
diff --git a/gas/config/tc-esp32ulp.c b/gas/config/tc-esp32ulp.c
@@ -48,6 +48,8 @@ int last_insn_size;
 extern struct obstack mempool;
 FILE *errorf;
 
+unsigned int dr_reg_rtccntl_base;
+
 /* Flags to set in the elf header */
 #define DEFAULT_FLAGS 0
 
@@ -117,18 +119,24 @@ size_t md_longopts_size = sizeof (md_longopts);
 int
 md_parse_option (int c, const char *arg)
 {
-//      printf("md_parse_option: arg - %s\n", arg);
   switch (c)
     {
     case OPTION_MCPU:
       {
 	if (strcasecmp (arg, "esp32") == 0)
 	  {
 	    ulp_cpu_type = CPU_TYPE_ESP32ULP;
+	    dr_reg_rtccntl_base = DR_REG_RTCCNTL_BASE_ESP32;
 	  }
 	else if (strcasecmp (arg, "esp32s2") == 0)
 	  {
 	    ulp_cpu_type = CPU_TYPE_ESP32ULP_S2;
+	    dr_reg_rtccntl_base = DR_REG_RTCCNTL_BASE_ESP32S2;
+	  }
+	else if (strcasecmp (arg, "esp32s3") == 0)
+	  {
+	    ulp_cpu_type = CPU_TYPE_ESP32ULP_S2;
+	    dr_reg_rtccntl_base = DR_REG_RTCCNTL_BASE_ESP32S3;
 	  }
 	else
 	  {
@@ -347,7 +355,9 @@ check_reg_range (fixS * fixP, long value)
 	{
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
 			_
-			("Register address out of range. Must be in range of 0..0x3ff or 0x3ff48000..0x3ff49000."));
+			("Register address out of range. Must be in range of %x..%x or %x..%x."),
+			0, DR_REG_MAX_DIRECT, DR_REG_RTCCNTL_BASE,
+			DR_REG_IO_MUX_BASE);
 	}
     }
   return result;

diff --git a/gas/config/tc-esp32ulp_esp32.c b/gas/config/tc-esp32ulp_esp32.c
@@ -149,8 +149,9 @@ esp32ulp_cmd_reg_rd_esp32 (Expr_Node * addr, Expr_Node * high,
 	}
       else
 	{
-	  error ("%s",
-		 "Register address out of range. Must be 0..0x3ff, or in range of 0x3ff48000 .. 0x3ff49000.");
+	  error
+	    ("Register address out of range. Must be %x..%x, or in range of %x..%x.",
+	     0, DR_REG_MAX_DIRECT, DR_REG_RTCCNTL_BASE, DR_REG_IO_MUX_BASE);
 	}
     }
   unsigned int local_op = I_RD_REG (addr_val, low_val, high_val);
@@ -183,8 +184,9 @@ esp32ulp_cmd_reg_wr_esp32 (Expr_Node * addr, Expr_Node * high,
 	}
       else
 	{
-	  error ("%s",
-		 "Register address out of range. Must be 0..0x3ff, or in range of 0x3ff48000 .. 0x3ff49000.");
+	  error
+	    ("Register address out of range. Must be %x..%x, or in range of %x..%x.",
+	     0, DR_REG_MAX_DIRECT, DR_REG_RTCCNTL_BASE, DR_REG_IO_MUX_BASE);
 	}
     }
   unsigned int local_op = I_WR_REG (addr_val, low_val, high_val, data_val);

diff --git a/gas/config/tc-esp32ulp_esp32s2.c b/gas/config/tc-esp32ulp_esp32s2.c
@@ -87,8 +87,9 @@ esp32ulp_cmd_reg_rd_esp32s2 (Expr_Node * addr, Expr_Node * high,
 	}
       else
 	{
-	  error ("%s",
-		 "Register address out of range. Must be 0..0x3ff, or in range of 0x3ff48000 .. 0x3ff49000.");
+	  error
+	    ("Register address out of range. Must be %x..%x, or in range of %x..%x.",
+	     0, DR_REG_MAX_DIRECT, DR_REG_RTCCNTL_BASE, DR_REG_IO_MUX_BASE);
 	}
     }
   unsigned int local_op = I_RD_REG (addr_val, low_val, high_val);
@@ -121,8 +122,9 @@ esp32ulp_cmd_reg_wr_esp32s2 (Expr_Node * addr, Expr_Node * high,
 	}
       else
 	{
-	  error ("%s",
-		 "Register address out of range. Must be 0..0x3ff, or in range of 0x3ff48000 .. 0x3ff49000.");
+	  error
+	    ("Register address out of range. Must be %x..%x, or in range of %x..%x.",
+	     0, DR_REG_MAX_DIRECT, DR_REG_RTCCNTL_BASE, DR_REG_IO_MUX_BASE);
 	}
     }
   unsigned int local_op = I_WR_REG (addr_val, low_val, high_val, data_val);

diff --git a/include/elf/esp32ulp.h b/include/elf/esp32ulp.h
@@ -108,13 +108,18 @@ START_RELOC_NUMBERS (elf_esp32ulp_reloc_type)
 #define	EF_ESP32ULP_PIC_FLAGS	(EF_ESP32ULP_PIC | EF_ESP32ULP_FDPIC)
 
 #define DR_REG_MAX_DIRECT                       0x3ff
-#define DR_REG_RTCCNTL_BASE                     0x3ff48000
-#define DR_REG_IO_MUX_BASE                      0x3ff49000
+#define DR_REG_RTCCNTL_BASE_ESP32               0x3ff48000
+#define DR_REG_RTCCNTL_BASE_ESP32S2             0x3f408000
+#define DR_REG_RTCCNTL_BASE_ESP32S3             0x60008000
 
+#define DR_REG_RTCCNTL_BASE dr_reg_rtccntl_base
+#define DR_REG_IO_MUX_BASE (dr_reg_rtccntl_base + 0x1000)
 
 #define CPU_TYPE_ESP32ULP                 		0 // --mcpu=esp32
-#define CPU_TYPE_ESP32ULP_S2                  	1 // --mcpu=esp32s2
+#define CPU_TYPE_ESP32ULP_S2                  	1 // --mcpu=esp32s2, --mcpu=esp32s3
 
 #define NEXT_INSTRUCTION_STEP  					4 // Step in bytes for next instruction
 
+extern unsigned int dr_reg_rtccntl_base;
+
 #endif /* _ELF_ESP32ULP_H */