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[Xtensa] Fix fp16 conversion #92

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gerekon
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@gerekon gerekon commented Mar 28, 2024

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@gerekon gerekon changed the title [Xtensa] Disable fp16 conversion intrinsics [Xtensa] Fix fp16 conversion Mar 28, 2024
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gerekon commented Mar 29, 2024

@andreisfr @sstefan1 PTAL
@kassane FYI

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I suggest using update_llc_test_checks.py for generating check lines. Otherwise LGTM!

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gerekon commented Apr 1, 2024

@sstefan1

I suggest using update_llc_test_checks.py for generating check lines. Otherwise LGTM!

Actually I used it to generate initial test case. But after that I removed instructions and left only ones related to conversion functions calls as it is done for ARM. But looks like that code is 9 years old, so it was written before the first version of update_llc_test_checks.py was implemented.

So. Ok. I will re-generate checks for easier maintenance in future.

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kassane commented Apr 1, 2024

This change didn't give me the error mentioned in the issue.

But, now:

$> ./out/zig-x86_64-linux-musl-baseline/zig cc -target xtensa-freestanding -mcpu=esp32 start.c
LLVM Emit Object... error: <unknown>:0: Undefined temporary symbol .LBB385_2

@gerekon gerekon changed the base branch from xtensa_release_17.0.1 to xtensa_release_18.1.2 October 22, 2024 11:48
@gerekon gerekon changed the base branch from xtensa_release_18.1.2 to xtensa_release_17.0.1 October 22, 2024 11:49
@gerekon gerekon changed the base branch from xtensa_release_17.0.1 to xtensa_release_18.1.2 October 22, 2024 11:52
@espressif-bot espressif-bot merged commit 256abfe into espressif:xtensa_release_18.1.2 Oct 22, 2024
10 of 16 checks passed
kassane added a commit to kassane/zig-esp-idf-sample that referenced this pull request Oct 22, 2024
with espressif/LLVM v18.1.2 - float fixed (esp32/s3)
ref.: espressif/llvm-project#92
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4 participants