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target/espressif: add riscv read only regs to the register list #6

target/espressif: add riscv read only regs to the register list

target/espressif: add riscv read only regs to the register list #6

Triggered via push April 4, 2024 10:08
Status Success
Total duration 3m 32s
Artifacts 3

ci_workflow.yml

on: push
Build OpenOCD  /  build-macos-x86
2m 57s
Build OpenOCD / build-macos-x86
Build OpenOCD  /  build-linux
1m 28s
Build OpenOCD / build-linux
Build OpenOCD  /  build-windows
2m 23s
Build OpenOCD / build-windows
Test OpenOCD  /  Test OpenOCD on MacOS
12s
Test OpenOCD / Test OpenOCD on MacOS
Test OpenOCD  /  Test OpenOCD on Linux
4s
Test OpenOCD / Test OpenOCD on Linux
Test OpenOCD  /  Test OpenOCD on Windows
15s
Test OpenOCD / Test OpenOCD on Windows
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Artifacts

Produced during runtime
Name Size
openocd-linux Expired
2.69 MB
openocd-macos-x86 Expired
2.56 MB
openocd-windows Expired
2.57 MB