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target/esp_riscv: add medeleg reg to esp32c6 and h2 #8

target/esp_riscv: add medeleg reg to esp32c6 and h2

target/esp_riscv: add medeleg reg to esp32c6 and h2 #8

Triggered via push April 12, 2024 19:49
Status Success
Total duration 6m 51s
Artifacts 3

ci_workflow.yml

on: push
Build OpenOCD  /  build-macos-x86
6m 12s
Build OpenOCD / build-macos-x86
Build OpenOCD  /  build-linux
1m 31s
Build OpenOCD / build-linux
Build OpenOCD  /  build-windows
2m 21s
Build OpenOCD / build-windows
Test OpenOCD  /  Test OpenOCD on MacOS
14s
Test OpenOCD / Test OpenOCD on MacOS
Test OpenOCD  /  Test OpenOCD on Linux
5s
Test OpenOCD / Test OpenOCD on Linux
Test OpenOCD  /  Test OpenOCD on Windows
12s
Test OpenOCD / Test OpenOCD on Windows
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Artifacts

Produced during runtime
Name Size
openocd-linux Expired
2.69 MB
openocd-macos-x86 Expired
2.56 MB
openocd-windows Expired
2.57 MB