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tcl/espressif: fix tab and space alignments
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@erhankur
erhankur committed Jul 18, 2024
1 parent be8cadb commit 47af42f
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Showing 9 changed files with 309 additions and 325 deletions.
29 changes: 12 additions & 17 deletions tcl/target/esp32.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -5,39 +5,34 @@
source [find target/esp_common.cfg]

# Target specific global variables
set _CHIPNAME "esp32"
set _CPUTAPID 0x120034e5
set _ESP_ARCH "xtensa"
set _ESP_SMP_TARGET 1
set _ESP_SMP_BREAK 1
set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004

if { [info exists ESP32_ONLYCPU] } {
echo "ESP32_ONLYCPU command will be deprecated! Use ESP_ONLYCPU instead."
set _ONLYCPU $ESP32_ONLYCPU
}
set _CHIPNAME "esp32"
set _CPUTAPID 0x120034e5
set _ESP_ARCH "xtensa"
set _ESP_SMP_TARGET 1
set _ESP_SMP_BREAK 1
set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004

# if not set until now, set as default dual core
if { ![info exists _ONLYCPU] } {
set _ONLYCPU 3
set _ONLYCPU 3
}

set _FLASH_VOLTAGE 3.3
if { [info exists ESP32_FLASH_VOLTAGE] } {
set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
}

# Set workarea address and size
# Keep in mind 32KB area (0x3FFF8000-0x3FFFFFFF) is reserved for the apptrace blocks
set _WA_ADDR 0x3FFE0000
set _WA_SIZE 0x18000
set _WA_ADDR 0x3FFE0000
set _WA_SIZE 0x18000

proc esp32_memprot_is_enabled { } {
return 0
return 0
}

proc esp32_soc_reset { } {
soft_reset_halt
soft_reset_halt
}

create_esp_target $_ESP_ARCH
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108 changes: 54 additions & 54 deletions tcl/target/esp32c2.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -5,70 +5,70 @@
source [find target/esp_common.cfg]

# Target specific global variables
set _CHIPNAME "esp32c2"
set _CPUTAPID 0x0000cc25
set _ESP_ARCH "riscv"
set _ONLYCPU 1
set _ESP_SMP_TARGET 0
set _ESP_SMP_BREAK 0
set _ESP_EFUSE_MAC_ADDR_REG 0x60008840
set _CHIPNAME "esp32c2"
set _CPUTAPID 0x0000cc25
set _ESP_ARCH "riscv"
set _ONLYCPU 1
set _ESP_SMP_TARGET 0
set _ESP_SMP_BREAK 0
set _ESP_EFUSE_MAC_ADDR_REG 0x60008840

# Set workarea address and size
# stub flasher may need a lot of memory in case of compressed writes to flash (~107KB):
# - for apptrace: 2x16KB up buffers + 32KB down buffer
# - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs
# TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data.
# In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one.
set _WA_ADDR 0x3FCA0000
set _WA_SIZE 0x24000
set _WA_ADDR 0x3FCA0000
set _WA_SIZE 0x24000

# Target specific functions should be implemented for each riscv chips.
proc esp32c2_wdt_disable { } {
# Halt event can occur during config phase (before "init" is done).
# Ignore it since mww commands don't work at that time.
if { [string compare [command mode] config] == 0 } {
return
}

# Timer Group 0 WDT
mww 0x6001f064 0x50D83AA1
mww 0x6001F048 0
# RTC WDT
mww 0x6000809C 0x50D83AA1
mww 0x60008084 0
# SWD
mww 0x600080A4 0x8F1D312A
mww 0x600080A0 0x84B00000
if { [string compare [command mode] config] == 0 } {
return
}

# Timer Group 0 WDT
mww 0x6001f064 0x50D83AA1
mww 0x6001F048 0
# RTC WDT
mww 0x6000809C 0x50D83AA1
mww 0x60008084 0
# SWD
mww 0x600080A4 0x8F1D312A
mww 0x600080A0 0x84B00000
}

proc esp32c2_soc_reset { } {
global _RISCV_DMCONTROL

# This procedure does "digital system reset", i.e. resets
# all the peripherals except for the RTC block.
# It is called from reset-assert-post target event callback,
# after assert_reset procedure was called.
# Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
# temporarily take it out of reset. Save the dmcontrol state before
# doing so.
riscv dmi_write $_RISCV_DMCONTROL 0x80000001
# Trigger the reset
mww 0x60008000 0x9c00a000
# Workaround for stuck in cpu start during calibration.
# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
mww 0x6001F068 0
# Wait for the reset to happen
sleep 10
poll
# Disable the watchdogs again
esp32c2_wdt_disable

# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
# We will clean allhalted state by resuming the core.
riscv dmi_write $_RISCV_DMCONTROL 0x40000001

# Put the hart back into reset state. Note that we need to keep haltreq set.
riscv dmi_write $_RISCV_DMCONTROL 0x80000003
# This procedure does "digital system reset", i.e. resets
# all the peripherals except for the RTC block.
# It is called from reset-assert-post target event callback,
# after assert_reset procedure was called.
# Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
# temporarily take it out of reset. Save the dmcontrol state before
# doing so.
riscv dmi_write $_RISCV_DMCONTROL 0x80000001
# Trigger the reset
mww 0x60008000 0x9c00a000
# Workaround for stuck in cpu start during calibration.
# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
mww 0x6001F068 0
# Wait for the reset to happen
sleep 10
poll
# Disable the watchdogs again
esp32c2_wdt_disable

# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
# We will clean allhalted state by resuming the core.
riscv dmi_write $_RISCV_DMCONTROL 0x40000001

# Put the hart back into reset state. Note that we need to keep haltreq set.
riscv dmi_write $_RISCV_DMCONTROL 0x80000003
}

proc esp32c2_memprot_is_enabled { } {
Expand Down Expand Up @@ -96,26 +96,26 @@ proc esp32c2_memprot_is_enabled { } {
riscv dmi_write $_RISCV_ABS_CMD 0x2203b3
set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]

set IRAM_LOW 0x40380000
set IRAM_HIGH 0x403C0000
set DRAM_LOW 0x3FCA0000
set DRAM_HIGH 0x3FCE0000
set IRAM_LOW 0x40380000
set IRAM_HIGH 0x403C0000
set DRAM_LOW 0x3FCA0000
set DRAM_HIGH 0x3FCE0000
set PMP_RWX 0x07
set PMP_RW 0x03
set PMP_RW 0x03

# The lock bit remains unset during the execution of the 2nd stage bootloader.
# Thus we do not perform a lock bit check for IRAM and DRAM regions.

# Check OpenOCD can write and execute from IRAM.
if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} {
if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
return 1
}
}

# Check OpenOCD can read/write entire DRAM region.
if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} {
if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
return 1
}
}
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114 changes: 57 additions & 57 deletions tcl/target/esp32c3.cfg
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Original file line number Diff line number Diff line change
Expand Up @@ -5,84 +5,84 @@
source [find target/esp_common.cfg]

# Target specific global variables
set _CHIPNAME "esp32c3"
set _CPUTAPID 0x00005c25
set _ESP_ARCH "riscv"
set _ONLYCPU 1
set _ESP_SMP_TARGET 0
set _ESP_SMP_BREAK 0
set _ESP_EFUSE_MAC_ADDR_REG 0x60008844
set _CHIPNAME "esp32c3"
set _CPUTAPID 0x00005c25
set _ESP_ARCH "riscv"
set _ONLYCPU 1
set _ESP_SMP_TARGET 0
set _ESP_SMP_BREAK 0
set _ESP_EFUSE_MAC_ADDR_REG 0x60008844

# Set workarea address and size
# stub flasher may need a lot of memory in case of compressed writes to flash (~107KB):
# - for apptrace: 2x16KB up buffers + 32KB down buffer
# - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs
# TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data.
# In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one.
set _WA_ADDR 0x3FC80000
set _WA_SIZE 0x24000
set _WA_ADDR 0x3FC80000
set _WA_SIZE 0x24000

# Target specific functions should be implemented for each riscv chips.
proc esp32c3_wdt_disable { } {
# Halt event can occur during config phase (before "init" is done).
# Ignore it since mww commands don't work at that time.
if { [string compare [command mode] config] == 0 } {
return
}
# Halt event can occur during config phase (before "init" is done).
# Ignore it since mww commands don't work at that time.
if { [string compare [command mode] config] == 0 } {
return
}

# Timer Group 0 & 1 WDTs
mww 0x6001f064 0x50D83AA1
mww 0x6001F048 0
mww 0x60020064 0x50D83AA1
mww 0x60020048 0
# RTC WDT
mww 0x600080a8 0x50D83AA1
mww 0x60008090 0
# SWD
mww 0x600080b0 0x8F1D312A
mww 0x600080ac 0x84B00000
# Timer Group 0 & 1 WDTs
mww 0x6001f064 0x50D83AA1
mww 0x6001F048 0
mww 0x60020064 0x50D83AA1
mww 0x60020048 0
# RTC WDT
mww 0x600080a8 0x50D83AA1
mww 0x60008090 0
# SWD
mww 0x600080b0 0x8F1D312A
mww 0x600080ac 0x84B00000
}

proc esp32c3_soc_reset { } {
global _RISCV_DMCONTROL

# This procedure does "digital system reset", i.e. resets
# all the peripherals except for the RTC block.
# It is called from reset-assert-post target event callback,
# after assert_reset procedure was called.
# Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
# temporarily take it out of reset. Save the dmcontrol state before
# doing so.
riscv dmi_write $_RISCV_DMCONTROL 0x80000001
# Trigger the reset
mww 0x60008000 0x9c00a000
# Workaround for stuck in cpu start during calibration.
# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
mww 0x6001F068 0
# Wait for the reset to happen
sleep 10
poll
# Disable the watchdogs again
esp32c3_wdt_disable
# This procedure does "digital system reset", i.e. resets
# all the peripherals except for the RTC block.
# It is called from reset-assert-post target event callback,
# after assert_reset procedure was called.
# Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
# temporarily take it out of reset. Save the dmcontrol state before
# doing so.
riscv dmi_write $_RISCV_DMCONTROL 0x80000001
# Trigger the reset
mww 0x60008000 0x9c00a000
# Workaround for stuck in cpu start during calibration.
# By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration
mww 0x6001F068 0
# Wait for the reset to happen
sleep 10
poll
# Disable the watchdogs again
esp32c3_wdt_disable

# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
# We will clean allhalted state by resuming the core.
riscv dmi_write $_RISCV_DMCONTROL 0x40000001
# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
# We will clean allhalted state by resuming the core.
riscv dmi_write $_RISCV_DMCONTROL 0x40000001

# Put the hart back into reset state. Note that we need to keep haltreq set.
riscv dmi_write $_RISCV_DMCONTROL 0x80000003
# Put the hart back into reset state. Note that we need to keep haltreq set.
riscv dmi_write $_RISCV_DMCONTROL 0x80000003
}

proc esp32c3_memprot_is_enabled { } {
# IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
if { [get_mmr_bit 0x600C10A8 0] != 0 } {
return 1
}
# DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
if { [get_mmr_bit 0x600C10C0 0] != 0 } {
return 1
}
return 0
# IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
if { [get_mmr_bit 0x600C10A8 0] != 0 } {
return 1
}
# DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
if { [get_mmr_bit 0x600C10C0 0] != 0 } {
return 1
}
return 0
}

create_esp_target $_ESP_ARCH
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