target/esp32p4: clear pending wdt interrupts and simplify the function

src/target/espressif/esp_riscv.c

@@ -596,7 +596,7 @@ int esp_riscv_resume(struct target *target, int current, target_addr_t address,
 static int esp_riscv_on_halt(struct target *target)
 {
  riscv_reg_t reg_value;
- if (riscv_get_register(target, &reg_value, GDB_REGNO_PC) == ERROR_OK)
+ if (riscv_get_register(target, &reg_value, GDB_REGNO_DPC) == ERROR_OK)
  LOG_TARGET_INFO(target, "Target halted, PC=0x%08" PRIX64 ", debug_reason=%08x",
  reg_value, target->debug_reason);
  esp_riscv_print_exception_reason(target);

tcl/target/esp32p4.cfg

@@ -34,25 +34,29 @@ set _WA_ADDR 0x8FF00000
 set _WA_SIZE 0x24000
 
 proc esp32p4_wdt_disable { } {
- global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0
+ # Halt event can occur during config phase (before "init" is done).
+ # Ignore it since mww commands don't work at that time.
+ if { [string compare [command mode] config] == 0 } {
+ return
+ }
 
  # Disable TG0 watchdog
- riscv dmi_write $_RISCV_SB_CS 0x40000
- riscv dmi_write $_RISCV_SB_ADDR0 0x500c2064
- riscv dmi_write $_RISCV_SB_DATA0 0x50D83AA1
-
- riscv dmi_write $_RISCV_SB_CS 0x40000
- riscv dmi_write $_RISCV_SB_ADDR0 0x500c2048
- riscv dmi_write $_RISCV_SB_DATA0 0
+ mww 0x500c2064 0x50D83AA1
+ mww 0x500c2048 0
+ # Clear TG0 wdt interrupt state
+ mww 0x500c207c 0x4
 
  # Disable TG1 watchdog
- riscv dmi_write $_RISCV_SB_CS 0x40000
- riscv dmi_write $_RISCV_SB_ADDR0 0x500c3064
- riscv dmi_write $_RISCV_SB_DATA0 0x50D83AA1
-
- riscv dmi_write $_RISCV_SB_CS 0x40000
- riscv dmi_write $_RISCV_SB_ADDR0 0x500c3048
- riscv dmi_write $_RISCV_SB_DATA0 0
+ mww 0x500c3064 0x50D83AA1
+ mww 0x500c3048 0
+ # Clear TG1 wdt interrupt state
+ mww 0x500c307c 0x4
+
+ # Disable RTC watchdog
+ mww 0x50116018 0x50D83AA1
+ mww 0x50116000 0
+ # Clear RTC wdt interrupt state
+ mww 0x50116030 0xC0000000
 }
 
 proc esp32p4_cpu0_wdt_disable { } {
@@ -63,15 +67,6 @@ proc esp32p4_cpu0_wdt_disable { } {
  esp32p4_wdt_disable
 }
 
-# TODO: Not in use. Will be removed.
-proc esp32p4_cpu1_wdt_disable { } {
- global _RISCV_DMCONTROL
-
- # Select hart1
- riscv dmi_write $_RISCV_DMCONTROL 0x80010001
- esp32p4_wdt_disable
-}
-
 proc esp32p4_soc_reset { } {
  global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0