ci: enable test_special for esp32c5

espressif · Oct 8, 2024 · 56e224d · 56e224d
1 parent ad4f125
commit 56e224d
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Showing 2 changed files with 6 additions and 5 deletions.
diff --git a/.gitlab/ci/test.yml b/.gitlab/ci/test.yml
@@ -261,7 +261,7 @@ tests_armhf_esp32c5:
  - job: build_linux_arm64_test
  variables:
  CHIP_NAME: "esp32c5"
- TEST_RUN_EXTRA_OPTS: "-i latest -b esp32c5-builtin -p test_*.*Single -e test_special*.*Single"
+ TEST_RUN_EXTRA_OPTS: "-i latest -b esp32c5-builtin -p test_*.*Single"
 
 tests_armhf_esp32c6:
  extends: .tests_armhf_master_riscv_template

diff --git a/testing/esp/test_special.py b/testing/esp/test_special.py
@@ -44,7 +44,7 @@ def _debug_image(self):
  self.run_to_bp_and_check(dbg.TARGET_STOP_REASON_BP, 'vTaskDelay', ['vTaskDelay0'])
  self.clear_bps()
 
- @skip_for_chip(['esp32s3', 'esp32'])
+ @skip_for_chip(['esp32s3', 'esp32', 'esp32c5'])
  def test_debugging_works_after_hw_reset(self):
  """
  This test checks that debugging works after HW reset.
@@ -77,8 +77,9 @@ def _do_test_bp_and_wp_set_by_program(self):
  self.run_to_bp_and_check_location(dbg.TARGET_STOP_REASON_SIGTRAP, 'target_bp_func1', 'target_wp_var1_1')
  # watchpoint hit on read var in 'target_bp_func1'
  self.run_to_bp_and_check_location(dbg.TARGET_STOP_REASON_SIGTRAP, 'target_bp_func1', 'target_wp_var1_2')
- # esp32c2 has only 2 hw triggers
- if testee_info.chip != "esp32c2":
+
+ # skip for targets not supporting 2 breakpoints + 2 watchpoints at the same time (for RISC-V 4 hardware triggers)
+ if testee_info.chip not in ["esp32c2", "esp32c5"]:
  # breakpoint at 'target_bp_func2' entry
  self.run_to_bp_and_check_location(dbg.TARGET_STOP_REASON_SIGTRAP, 'target_bp_func2', 'target_bp_func2')
  # watchpoint hit on write var in 'target_bp_func2'
@@ -310,7 +311,7 @@ def test_gdb_regs_mapping(self):
  """
  # should fail for any new chip.
  # just to be sure that this test is revised when new chip support is added
- self.fail_if_not_hw_id([r'esp32-[.]*', r'esp32s2-[.]*', r'esp32c2-[.]*', r'esp32c3-[.]*', r'esp32s3-[.]*', r'esp32c6-[.]*', r'esp32h2-[.]*'])
+ self.fail_if_not_hw_id([r'esp32-[.]*', r'esp32s2-[.]*', r'esp32c2-[.]*', r'esp32c3-[.]*', r'esp32s3-[.]*', r'esp32c6-[.]*', r'esp32h2-[.]*', r'esp32c5-[.]*'])
  regs = self.gdb.get_reg_names()
  i = 10