target: Add initial support for ESP32-C5

src/rtos/FreeRTOS.c

@@ -225,6 +225,23 @@ static const struct freertos_params freertos_params_list[] = {
  NULL,
  rtos_freertos_riscv_pick_stacking_info, /* fn to pick stacking_info */
  },
+ {
+ "esp32c5", /* target_name */
+ 4, /* thread_count_width; */
+ 4, /* pointer_width; */
+ 16, /* list_next_offset; */
+ 8, /* list_end_offset; */
+ 20, /* list_width; */
+ 8, /* list_elem_next_offset; */
+ 12, /* list_elem_content_offset */
+ 0, /* thread_stack_offset; */
+ 52, /* thread_name_offset; */
+ 4, /* thread_counter_width */
+ NULL, /* stacking_info */
+ NULL,
+ NULL,
+ rtos_freertos_riscv_pick_stacking_info, /* fn to pick stacking_info */
+ },
 };
 
 #define FREERTOS_NUM_PARAMS ARRAY_SIZE(freertos_params_list)

src/target/espressif/CMakeLists.txt

@@ -17,6 +17,7 @@ target_sources(espressif PRIVATE
  esp32c6.c
  esp32h2.c
  esp32p4.c
+ esp32c5.c
  esp.c
  esp.h
  esp_riscv.c

src/target/espressif/Makefile.am

@@ -16,6 +16,7 @@ noinst_LTLIBRARIES += %D%/libespressif.la
  %D%/esp32c3.c \
  %D%/esp32c6.c \
  %D%/esp32p4.c \
+ %D%/esp32c5.c \
  %D%/esp.c \
  %D%/esp.h \
  %D%/esp_riscv.c \

src/target/espressif/esp32c5.c

@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ * ESP32-C5 target for OpenOCD *
+ * Copyright (C) 2024 Espressif Systems Ltd. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/command.h>
+#include <helper/bits.h>
+#include <target/target.h>
+#include <target/target_type.h>
+#include <target/register.h>
+#include <target/semihosting_common.h>
+#include <target/riscv/debug_defines.h>
+
+#include "esp_semihosting.h"
+#include "esp_riscv_apptrace.h"
+#include "esp_riscv.h"
+
+/* max supported hw breakpoint and watchpoint count */
+#define ESP32C5_BP_NUM 3
+#define ESP32C5_WP_NUM 3
+
+/* ASSIST_DEBUG registers */
+#define ESP32C5_ASSIST_DEBUG_CPU0_MON_REG 0xFFFFFFFF//0x600C2000
+
+
+static const struct esp_semihost_ops esp32c5_semihost_ops = {
+ .prepare = NULL,
+ .post_reset = esp_semihosting_post_reset
+};
+
+static const struct esp_flash_breakpoint_ops esp32c5_flash_brp_ops = {
+ .breakpoint_add = esp_algo_flash_breakpoint_add,
+ .breakpoint_remove = esp_algo_flash_breakpoint_remove
+};
+
+static const char *esp32c5_csrs[] = {
+ "mideleg", "medeleg", "mie", "mip",
+};
+
+static int esp32c5_target_create(struct target *target, Jim_Interp *interp)
+{
+ struct esp_riscv_common *esp_riscv = calloc(1, sizeof(*esp_riscv));
+ if (!esp_riscv)
+ return ERROR_FAIL;
+
+ target->arch_info = esp_riscv;
+
+ esp_riscv->assist_debug_cpu0_mon_reg = ESP32C5_ASSIST_DEBUG_CPU0_MON_REG;
+ esp_riscv->assist_debug_cpu_offset = 0;
+
+ esp_riscv->max_bp_num = ESP32C5_BP_NUM;
+ esp_riscv->max_wp_num = ESP32C5_WP_NUM;
+
+ esp_riscv->rtccntl_reset_state_reg = 0;//ESP32C5_RTCCNTL_RESET_STATE_REG;
+ esp_riscv->print_reset_reason = NULL;//&esp32c5_print_reset_reason;
+ esp_riscv->existent_csrs = esp32c5_csrs;
+ esp_riscv->existent_csr_size = ARRAY_SIZE(esp32c5_csrs);
+
+ if (esp_riscv_alloc_trigger_addr(target) != ERROR_OK)
+ return ERROR_FAIL;
+
+ riscv_info_init(target, &esp_riscv->riscv);
+
+ return ERROR_OK;
+}
+
+static int esp32c5_init_target(struct command_context *cmd_ctx,
+ struct target *target)
+{
+ int ret = riscv_target.init_target(cmd_ctx, target);
+ if (ret != ERROR_OK)
+ return ret;
+
+ target->semihosting->user_command_extension = esp_semihosting_common;
+
+ struct esp_riscv_common *esp_riscv = target_to_esp_riscv(target);
+
+ ret = esp_riscv_init_arch_info(cmd_ctx,
+ target,
+ esp_riscv,
+ &esp32c5_flash_brp_ops,
+ &esp32c5_semihost_ops);
+ if (ret != ERROR_OK)
+ return ret;
+
+ return ERROR_OK;
+}
+
+static const struct command_registration esp32c5_command_handlers[] = {
+ {
+ .usage = "",
+ .chain = riscv_command_handlers,
+ },
+ {
+ .name = "esp",
+ .usage = "",
+ .chain = esp_riscv_command_handlers,
+ },
+ {
+ .name = "esp",
+ .usage = "",
+ .chain = esp32_apptrace_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct target_type esp32c5_target = {
+ .name = "esp32c5",
+
+ .target_create = esp32c5_target_create,
+ .init_target = esp32c5_init_target,
+ .deinit_target = esp_riscv_deinit_target,
+ .examine = esp_riscv_examine,
+
+ /* poll current target status */
+ .poll = esp_riscv_poll,
+
+ .halt = riscv_halt,
+ .resume = esp_riscv_resume,
+ .step = riscv_openocd_step,
+
+ .assert_reset = riscv_assert_reset,
+ .deassert_reset = riscv_deassert_reset,
+
+ .read_memory = esp_riscv_read_memory,
+ .write_memory = esp_riscv_write_memory,
+
+ .checksum_memory = riscv_checksum_memory,
+
+ .get_gdb_arch = riscv_get_gdb_arch,
+ .get_gdb_reg_list = riscv_get_gdb_reg_list,
+ .get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
+
+ .add_breakpoint = esp_riscv_breakpoint_add,
+ .remove_breakpoint = esp_riscv_breakpoint_remove,
+
+ .add_watchpoint = riscv_add_watchpoint,
+ .remove_watchpoint = riscv_remove_watchpoint,
+ .hit_watchpoint = esp_riscv_hit_watchpoint,
+
+ .arch_state = riscv_arch_state,
+
+ .run_algorithm = esp_riscv_run_algorithm,
+ .start_algorithm = esp_riscv_start_algorithm,
+ .wait_algorithm = esp_riscv_wait_algorithm,
+
+ .commands = esp32c5_command_handlers,
+
+ .address_bits = riscv_xlen_nonconst,
+};

src/target/target.c

@@ -94,6 +94,7 @@ static struct target_type *target_types[] = {
  &esp32h2_target,
  &esp32c3_target,
  &esp32c6_target,
+ &esp32c5_target,
  &esp32p4_target,
  &or1k_target,
  &quark_x10xx_target,

src/target/target_type.h

@@ -339,6 +339,7 @@ extern struct target_type esp32h2_target;
 extern struct target_type esp32c3_target;
 extern struct target_type esp32c6_target;
 extern struct target_type esp32p4_target;
+extern struct target_type esp32c5_target;
 extern struct target_type fa526_target;
 extern struct target_type feroceon_target;
 extern struct target_type hla_target;

tcl/board/esp32c5-bridge.cfg

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C5 connected via ESP USB Bridge board
+#
+# For example, OpenOCD can be started for ESP32-C5 debugging on
+#
+# openocd -f board/esp32c5-bridge.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_bridge.cfg]
+# ESP32C5 chip id defined in the idf esp_chip_model_t
+espusbjtag chip_id 23
+# Source the ESP32-C5 configuration file
+source [find target/esp32c5.cfg]

tcl/board/esp32c5-builtin.cfg

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C5 connected via builtin USB-JTAG adapter.
+#
+# For example, OpenOCD can be started for ESP32-C5 debugging on
+#
+# openocd -f board/esp32c5-builtin.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-C5 configuration file
+source [find target/esp32c5.cfg]

tcl/board/esp32c5-ftdi.cfg

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Example OpenOCD configuration file for ESP32-C5 connected via ESP-Prog.
+#
+# For example, OpenOCD can be started for ESP32-C5 debugging on
+#
+# openocd -f board/esp32c5-ftdi.cfg
+#
+
+# Source the JTAG interface configuration file
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+# Source the ESP32-C5 configuration file
+source [find target/esp32c5.cfg]

tcl/esp-config-schema.json

@@ -134,6 +134,7 @@
  "esp32s3",
  "esp32c2",
  "esp32c3",
+ "esp32c5",
  "esp32c6",
  "esp32h2",
  "esp32p4"

tcl/esp-config.json

@@ -6,6 +6,7 @@
  { "id": "esp32s3", "name": "ESP32-S3" },
  { "id": "esp32c2", "name": "ESP32-C2" },
  { "id": "esp32c3", "name": "ESP32-C3" },
+ { "id": "esp32c5", "name": "ESP32-C5" },
  { "id": "esp32c6", "name": "ESP32-C6" },
  { "id": "esp32h2", "name": "ESP32-H2" },
  { "id": "esp32p4", "name": "ESP32-P4" }
@@ -143,6 +144,30 @@
  "board/esp32c3-bridge.cfg"
  ]
  },
+ {
+ "name": "ESP32-C5 chip (via builtin USB-JTAG)",
+ "description": "ESP32-C5 debugging via builtin USB-JTAG",
+ "target": "esp32c5",
+ "config_files": [
+ "board/esp32c5-builtin.cfg"
+ ]
+ },
+ {
+ "name": "ESP32-C5 chip (via ESP-PROG)",
+ "description": "ESP32-C5 debugging via ESP-PROG board",
+ "target": "esp32c5",
+ "config_files": [
+ "board/esp32c5-ftdi.cfg"
+ ]
+ },
+ {
+ "name": "ESP32-C5 chip (via ESP-PROG-2)",
+ "description": "ESP32-C5 debugging via ESP-PROG-2 board",
+ "target": "esp32c5",
+ "config_files": [
+ "board/esp32c5-bridge.cfg"
+ ]
+ },
  {
  "name": "ESP32-C6 chip (via builtin USB-JTAG)",
  "description": "ESP32-C6 debugging via builtin USB-JTAG",