ESP32S3 openocd debugging (OCD-406)

[skj2021]

I am trying to configure openocd for debugging with ESP32S3 module. I am using ESP32-S3-DevKitC-1. I am using eclipse for my debugging. My configuration to start server on cmd prompt is openocd.exe -f interface\esp_usb_jtag.cfg -f board\esp32s3-builtin.cfg and I use GDB Hardware debugging onn eclipse to set the gdb client. GDB command xtensa-esp32s3-elf-gdb and GDB Connection STring is localhost:3333.
But when I run debug configuration I get
Error: esp_usb_jtag: usb sent only 0 out of 31 bytes.
Error: missing data from bitq interface
Error: esp_usb_jtag: usb sent only 0 out of 50 bytes.
Error: missing data from bitq interface
Error: Failed to exec JTAG queue!
Error: Failed to read debug stubs address location (-104)!

I understand that all the openocd features are not supported currently for ESP32S3 but I assume that the basic debugging part is supported. So i was expecting it to work. I am not sure if I am missing any configuration? Any inputs on this? Thanks.

[gerekon]

Hi @skj2021

It looks like problem with driver on Winodws. Can you try to remove it and install using IDF Tools Installer?

[NateZimmer]

Out of curiosity, did you find the documentation for that command? openocd.exe -f interface\esp_usb_jtag.cfg -f board\esp32s3-builtin.cfg The latest documentation is wrong at https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/index.html#run-openocd citing files that don't exist in the latest openocd release by espressif or in the latest IDF Tools Installer (unlike your command which is correct). So... hunting correct documentation
I'm stuck a bit earlier in the process. I see the CDC USB driver but I can't find any interface for JTAG despite installing the latest tools. Nothing visible via zadig either.

[gerekon]

@NateZimmer

citing files that don't exist in the latest openocd release

Sorry for that. This is a mistake in docs. There are two board config files for S3:

• board\esp32s3-builtin.cfg for working via builtin USB_JTAG
• board\esp32s3-ftdi.cfg for working via externally connected FTDI-based probe like ESP-PROG

I see the CDC USB driver but I can't find any interface for JTAG despite installing the latest tools. Nothing visible via zadig either.

Maybe it was mentioned as Unknown device in the system because driver have not been installed properly?

BTW. Could you post efuse configs for your board (output of espefuse.py -p COMxx summary)?

[NateZimmer]

@gerekon

Can you show me what its suppose to look like in device manager? I've tried 3 S3s on 2 different PCs. Is there a fuse you have to SET to get it to work? Looks like all my fuses are pretty much 0

df_4_3_1>espefuse.py -p COM3 summary
Connecting...
Detecting chip type... ESP32-S3(beta3)
espefuse.py v3.1-dev
EFUSE_NAME (Block)                       Description  = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Config fuses:
DIS_RTC_RAM_BOOT (BLOCK0)                Disables boot from RTC RAM                         = False R/W (0b0)
DIS_ICACHE (BLOCK0)                      Disables ICache                                    = False R/W (0b0)
DIS_DCACHE (BLOCK0)                      Disables DCache                                    = False R/W (0b0)
DIS_DOWNLOAD_ICACHE (BLOCK0)             Disables Icache when SoC is in Download mode       = False R/W (0b0)
DIS_DOWNLOAD_DCACHE (BLOCK0)             Disables Dcache when SoC is in Download mode       = False R/W (0b0)
DIS_FORCE_DOWNLOAD (BLOCK0)              Disables forcing chip into Download mode           = False R/W (0b0)
DIS_CAN (BLOCK0)                         Disables the TWAI Controller hardware              = False R/W (0b0)
DIS_APP_CPU (BLOCK0)                     Disables APP CPU                                   = False R/W (0b0)
FLASH_TPUW (BLOCK0)                      Configures flash startup delay after SoC power-up, = 0 R/W (0x0)
                                          unit is (ms/2). When the value is 15, delay is 7.
                                         5 ms
DIS_LEGACY_SPI_BOOT (BLOCK0)             Disables Legacy SPI boot mode                      = False R/W (0b0)
UART_PRINT_CHANNEL (BLOCK0)              Selects the default UART for printing boot msg     = UART0 R/W (0b0)
FLASH_ECC_MODE (BLOCK0)                  Configures the ECC mode for SPI flash
   = 16-byte to 18-byte mode R/W (0b0)
DIS_USB_DOWNLOAD_MODE (BLOCK0)           Disables USB OTG download feature in UART download = False R/W (0b0)
                                          boot mode
UART_PRINT_CONTROL (BLOCK0)              Sets the default UART boot message output mode     = Enabled R/W (0b00)
FLASH_TYPE (BLOCK0)                      Selects SPI flash type                             = 4 data lines R/W (0b0)
FLASH_PAGE_SIZE (BLOCK0)                 Sets the size of flash page                        = 0 R/W (0b00)
FLASH_ECC_EN (BLOCK0)                    Enables ECC in Flash boot mode                     = False R/W (0b0)
FORCE_SEND_RESUME (BLOCK0)               Forces ROM code to send an SPI flash resume comman = False R/W (0b0)
                                         d during SPI boot
BLOCK_USR_DATA (BLOCK3)                  User data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Efuse fuses:
WR_DIS (BLOCK0)                          Disables programming of individual eFuses          = 0 R/W (0x00000000)
RD_DIS (BLOCK0)                          Disables software reading from BLOCK4-10           = 0 R/W (0b0000000)

Identity fuses:
SECURE_VERSION (BLOCK0)                  Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000)
                                         ure)
MAC (BLOCK1)                             Factory MAC Address
   = 00:00:00:00:00:00: (OK) R/W
WAFER_VERSION (BLOCK1)                   WAFER version                                      = A R/W (0b000)
PKG_VERSION (BLOCK1)                     ??? Package version                                = ESP32-S3 R/W (0x0)
BLOCK1_VERSION (BLOCK1)                  ??? BLOCK1 efuse version                           = 0 R/W (0b000)
OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors):   ??? Optional unique 128-bit ID
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2_VERSION (BLOCK2)                  ??? Version of BLOCK2                              = No calibration R/W (0b000)

Security fuses:
SOFT_DIS_JTAG (BLOCK0)                   Software disables JTAG by programming odd number o = 0 R/W (0b000)
                                         f 1 bit(s). JTAG can be re-enabled via HMAC periph
                                         eral
HARD_DIS_JTAG (BLOCK0)                   Hardware disables JTAG permanently                 = False R/W (0b0)
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0)     Disables flash encryption when in download boot mo = False R/W (0b0)
                                         des
SPI_BOOT_CRYPT_CNT (BLOCK0)              Enables encryption and decryption, when an SPI boo = Disable R/W (0b000)
                                         t mode is set. Enabled when 1 or 3 bits are set,di
                                         sabled otherwise
SECURE_BOOT_KEY_REVOKE0 (BLOCK0)         Revokes use of secure boot key digest 0            = False R/W (0b0)
SECURE_BOOT_KEY_REVOKE1 (BLOCK0)         Revokes use of secure boot key digest 1            = False R/W (0b0)
SECURE_BOOT_KEY_REVOKE2 (BLOCK0)         Revokes use of secure boot key digest 2            = False R/W (0b0)
KEY_PURPOSE_0 (BLOCK0)                   KEY0 purpose                                       = USER R/W (0x0)
KEY_PURPOSE_1 (BLOCK0)                   KEY1 purpose                                       = USER R/W (0x0)
KEY_PURPOSE_2 (BLOCK0)                   KEY2 purpose                                       = USER R/W (0x0)
KEY_PURPOSE_3 (BLOCK0)                   KEY3 purpose                                       = USER R/W (0x0)
KEY_PURPOSE_4 (BLOCK0)                   KEY4 purpose                                       = USER R/W (0x0)
KEY_PURPOSE_5 (BLOCK0)                   KEY5 purpose                                       = USER R/W (0x0)
SECURE_BOOT_EN (BLOCK0)                  Enables secure boot                                = False R/W (0b0)
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0)   Enables aggressive secure boot key revocation mode = False R/W (0b0)
DIS_DOWNLOAD_MODE (BLOCK0)               Disables all Download boot modes                   = False R/W (0b0)
ENABLE_SECURITY_DOWNLOAD (BLOCK0)        Enables secure UART download mode (read/write flas = False R/W (0b0)
                                         h only)
BLOCK_KEY0 (BLOCK4)(0 errors):
  Purpose: USER
  Encryption key0 or user data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY1 (BLOCK5)(0 errors):
  Purpose: USER
  Encryption key1 or user data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY2 (BLOCK6)(0 errors):
  Purpose: USER
  Encryption key2 or user data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY3 (BLOCK7)(0 errors):
  Purpose: USER
  Encryption key3 or user data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY4 (BLOCK8)(0 errors):
  Purpose: USER
  Encryption key4 or user data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_KEY5 (BLOCK9)(0 errors):
  Purpose: USER
  Encryption key5 or user data
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK_SYS_DATA2 (BLOCK10)                System data (part 2)
   = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Spi_Pad_Config fuses:
SPI_PAD_CONFIG_CLK (BLOCK1)              SPI CLK pad                                        = 0 R/W (0b000000)
SPI_PAD_CONFIG_Q (BLOCK1)                SPI Q (D1) pad                                     = 0 R/W (0b000000)
SPI_PAD_CONFIG_D (BLOCK1)                SPI D (D0) pad                                     = 0 R/W (0b000000)
SPI_PAD_CONFIG_CS (BLOCK1)               SPI CS pad                                         = 0 R/W (0b000000)
SPI_PAD_CONFIG_HD (BLOCK1)               SPI HD (D3) pad                                    = 0 R/W (0b000000)
SPI_PAD_CONFIG_WP (BLOCK1)               SPI WP (D2) pad                                    = 0 R/W (0b000000)
SPI_PAD_CONFIG_DQS (BLOCK1)              SPI DQS pad                                        = 0 R/W (0b000000)
SPI_PAD_CONFIG_D4 (BLOCK1)               SPI D4 pad                                         = 0 R/W (0b000000)
SPI_PAD_CONFIG_D5 (BLOCK1)               SPI D5 pad                                         = 0 R/W (0b000000)
SPI_PAD_CONFIG_D6 (BLOCK1)               SPI D6 pad                                         = 0 R/W (0b000000)
SPI_PAD_CONFIG_D7 (BLOCK1)               SPI D7 pad                                         = 0 R/W (0b000000)

Usb Config fuses:
DIS_USB (BLOCK0)                         Disables the USB OTG hardware                      = False R/W (0b0)
USB_EXCHG_PINS (BLOCK0)                  Exchanges USB D+ and D- pins                       = False R/W (0b0)
EXT_PHY_ENABLE (BLOCK0)                  Enables external USB PHY                           = False R/W (0b0)
BTLC_GPIO_ENABLE (BLOCK0)                Enables BTLC GPIO                                  = 0 R/W (0b00)

Vdd_Spi Config fuses:
VDD_SPI_XPD (BLOCK0)                     The VDD_SPI regulator is powered on                = False R/W (0b0)
VDD_SPI_TIEH (BLOCK0)                    The VDD_SPI power supply voltage at reset          = Connect to 1.8V LDO R/W (0b0)
VDD_SPI_FORCE (BLOCK0)                   Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0)
                                         ure VDD_SPI LDO
PIN_POWER_SELECTION (BLOCK0)             Sets default power supply for GPIO33..37           = VDD3P3_CPU R/W (0b0)

Wdt Config fuses:
WDT_DELAY_SEL (BLOCK0)                   Selects RTC WDT timeout threshold at startup       = 0 R/W (0b00)

Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO
GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V).


idf_4_3_1>espefuse.py -p COM3 dump
Connecting....
Detecting chip type... ESP32-S3(beta3)
BLOCK0          (                ) [0 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
MAC_SPI_8M_0    (BLOCK1          ) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_SYS_DATA  (BLOCK2          ) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_USR_DATA  (BLOCK3          ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_KEY0      (BLOCK4          ) [4 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_KEY1      (BLOCK5          ) [5 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_KEY2      (BLOCK6          ) [6 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_KEY3      (BLOCK7          ) [7 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_KEY4      (BLOCK8          ) [8 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_KEY5      (BLOCK9          ) [9 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK_SYS_DATA2 (BLOCK10         ) [10] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

Unfortunately, you can't seem to be able to read all of block 0, so I can't guarantee the fuse status of fuses relating to USB JTAG

[gerekon]

@NateZimmer

Unfortunately, you can't seem to be able to read all of block 0, so I can't guarantee the fuse status of fuses relating to USB JTAG

Yes. It seems that espefuse.py from IDF 4.3 does not support S3 efuses completely.

In any case I think if you see CDC USB device you should also have USB_JTAG. Could you post screenshot with list of USB devices shown by zadig?

BTW, Could you post output of openocd.exe -f board\esp32s3-builtin.cfg -d3?

[NateZimmer]

So the example code loaded on these things from digikey breaks the USB debug until the program is erased. After loading over serial/uart I get my 2 interfaces in zadig.
Only thing I got working so far is attach debugging. When I try to load over JTAG I get

Haven't tried the 4.4 branch yet. Example of debug working:

So... starting to get there. Startup i'm using:

mon reset halt
mon program_esp build/blink.bin} 0x10000 verify
mon reset halt
flushregs
set remote hardware-watchpoint-limit 2

If I get rid of the program load I can at least successfully debug attach

What I assume everyone is shooting for is to be able to view the serial monitor over CDC enumeration (currently it doesn't and its set for bootloader?) then to be able to load over JTAG (not currently working) .. so.. not quite ready for prime time yet?

[gerekon]

to be able to load over JTAG

It will be released soon.

[gerekon]

Closed by dbede94 and 9e06f3e