Unable to debug ESP32-C3-DevKitC-02v1.1 on M1 MacOS using VS Code + ESP-IDF (But Flashing Code Works) (OCD-1063)

[Shu244]

Development Kit

ESP32-C3-DevKitC-02v1.1

Module or chip used

ESP32-C3-WROOM-02

Debug Adapter

Built-in JTAG

OpenOCD version

v0.12.0-esp32-20241016

Operating System

M1 Mac, MacOS 14.6.1

Using an IDE ?

VS Code with ESP-IDF extension

OpenOCD command line

Using VS Code built in debug button (settings below)

JTAG Clock Speed

N/A

ESP-IDF version

v5.4.0

Problem Description

I am unable to debug my ESP32 dev kit using the settings

{
    "C_Cpp.intelliSenseEngine": "default",
    "idf.espIdfPath": "/Users/shu/esp/esp-idf",
    "idf.openOcdConfigs": [
        "board/esp32c3-builtin.cfg"
    ],
    "idf.port": "/dev/tty.usbserial-110",
    "idf.toolsPath": "/Users/shu/.espressif",
    "files.associations": {
        "led_strip.h": "c"
    },
    "idf.flashType": "UART"
}

I get the error:

Open On-Chip Debugger v0.12.0-esp32-20241016 (2024-10-16-14:27)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
debug_level: 2

Info : only one transport option; autoselecting 'jtag'

Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Info : esp_usb_jtag: capabilities descriptor set to 0x2000

Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections

❌ Error: esp_usb_jtag: could not find or open device!

❌ /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/target/esp_common.cfg:9: Error: 
at file "/Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/target/esp_common.cfg", line 9
Error: [esp32c3] Unsupported DTM version: -1
Error: [esp32c3] Could not identify target type.

For assistance with OpenOCD errors, please refer to our Troubleshooting FAQ: https://github.com/espressif/openocd-esp32/wiki/Troubleshooting-FAQ
OpenOCD Exit with non-zero error code 1
[Stopped] : OpenOCD Server

I am able to flash the MCU, but I am unable to debug. I have been trying to get the debugging to work for many days and read a lot of the Espressif documentation, but none seem to help. Any help is greatly appreciated. Thank you!

Debug Logs

No response

Expected behavior

Enter debug mode.

Screenshots

No response

[erhankur]

@Shu244 can you explain your jtag connection?

https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/api-guides/jtag-debugging/configure-builtin-jtag.html#configure-esp32-c3-built-in-jtag-interface

You need a breakout cable like this: https://www.adafruit.com/product/4448

[Shu244]

Hi @erhankur thank you for taking a look. I was reading this doc

The quickest and most convenient way to start with JTAG debugging is through a USB cable connected to the D+/D- USB pins of ESP32-C3. No need for an external JTAG adapter and extra wiring/cable to connect JTAG to ESP32-C3.

I assumed that this means I can use the existing onboard micro USB on the dev board for debugging. Is this not the case?

Thinking about it more, I suppose the USB is connected to the USB-UART bridge and connected to UART pins rather than the MCU's USB D-/D+ pins. I wish the documents were a little more clear about explicitly needing a separate USB wire.

[erhankur]

@Shu244 do you still need some help from our side?

[Shu244]

Sorry for the delay @erhankur . I am still having a lot of trouble trying to get the debugger to work.

The following is the output when I clear the flash and try to start the debugger:

Open On-Chip Debugger v0.12.0-esp32-20241016 (2024-10-16-14:27)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
debug_level: 2

Info : only one transport option; autoselecting 'jtag'
Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Info : esp_usb_jtag: capabilities descriptor set to 0x2000

Info : Listening on port 6666 for tcl connections

Info : Listening on port 4444 for telnet connections

Info : esp_usb_jtag: serial (24:58:7C:AC:B8:8C)

Info : esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255

Info : clock speed 40000 kHz

Info : JTAG tap: esp32c3.tap0 tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)

Info : [esp32c3] datacount=2 progbufsize=16

Info : [esp32c3] Examined RISC-V core; found 1 harts
Info : [esp32c3]  XLEN=32, misa=0x40101104

Info : [esp32c3] Examination succeed
Info : [esp32c3] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Info : [esp32c3] Hart unexpectedly reset!

Info : [esp32c3] Reset cause (7) - (Main WDT0 core reset)

Thank you for helping, I have been stuck here and been unable to make progress.

[erhankur]

Before debugging, you first need to load the application. How do you do that?
I suggest starting with the hello-world example from the command line within the ESP-IDF environment. Then, once you’re sure your hw and sw setup is ready, switch to the IDE and try debugging there. After that, it’s mainly a matter of playing with the IDE settings.

From one terminal

cd hello_world
idf.py set-target esp32c3
idf.py flash
idf.py openocd

From the other terminal

idf.py gdb
# idf.py gdbgui or idf.py gdbtui depends on your choice

[Shu244]

Hi @erhankur I am using VS Code with ESP IDF extension. I am starting with the Blinky example and was able to flash the MCU and see the LED blinking. I feel confident the hardware and software is now set up properly. To start debugging, I am simply using the debug button in the IDE.

[erhankur]

Can you share your settings.json?

In the meantime you can add "idf.openOcdDebugLevel": 3, and send us OpenOCD logs. You should see the logs at the output tab.

[Shu244]

@erhankur here is my settings.json:

{
    "C_Cpp.intelliSenseEngine": "default",
    "idf.espIdfPath": "/Users/shuhao/esp/esp-idf",
    "idf.openOcdConfigs": [
        "board/esp32c3-builtin.cfg"
    ],
    "idf.port": "/dev/tty.usbmodem11201",
    "idf.toolsPath": "/Users/shuhao/.espressif",
    "files.associations": {
        "led_strip.h": "c"
    },
    "idf.flashType": "UART"
}

Here are the logs:

pen On-Chip Debugger v0.12.0-esp32-20241016 (2024-10-16-14:27)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
User : 3 1 options.c:52 configuration_output_handler(): debug_level: 3User : 4 1 options.c:52 configuration_output_handler(): 
Debug: 5 1 options.c:346 parse_cmdline_args(): ARGV[0] = "openocd"
Debug: 6 1 options.c:346 parse_cmdline_args(): ARGV[1] = "-d3"
Debug: 7 1 options.c:346 parse_cmdline_args(): ARGV[2] = "-f"
Debug: 8 1 options.c:346 parse_cmdline_args(): ARGV[3] = "board/esp32c3-builtin.cfg"
Debug: 9 1 options.c:233 add_default_dirs(): bindir=/builds/idf/openocd-esp32/_build/../openocd-esp32/bin
Debug: 10 1 options.c:234 add_default_dirs(): pkgdatadir=/builds/idf/openocd-esp32/_build/../openocd-esp32/share/openocd
Debug: 11 1 options.c:235 add_default_dirs(): exepath=/Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/bin
Debug: 12 1 options.c:236 add_default_dirs(): bin2data=../share/openocd
Debug: 13 1 configuration.c:33 add_script_search_dir(): adding /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts
Debug: 14 1 configuration.c:33 add_script_search_dir(): adding /Users/shuhao/Library/Preferences/org.openocd
Debug: 15 1 configuration.c:33 add_script_search_dir(): adding /Users/shuhao/.config/openocd
Debug: 16 1 configuration.c:33 add_script_search_dir(): adding /Users/shuhao/.openocd
Debug: 17 1 configuration.c:33 add_script_search_dir(): adding /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/bin/../share/openocd/site

Debug: 18 1 configuration.c:33 add_script_search_dir(): adding /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/bin/../share/openocd/scripts
Debug: 19 1 command.c:152 script_debug(): command - ocd_find board/esp32c3-builtin.cfg
Debug: 20 1 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/board/esp32c3-builtin.cfg

Debug: 21 1 command.c:152 script_debug(): command - ocd_find interface/esp_usb_jtag.cfg

Debug: 22 1 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/interface/esp_usb_jtag.cfg

Debug: 23 2 command.c:152 script_debug(): command - adapter driver esp_usb_jtag
Info : 24 2 transport.c:106 allow_transports(): only one transport option; autoselecting 'jtag'

Debug: 25 2 command.c:152 script_debug(): command - espusbjtag vid_pid 0x303a 0x1001
Info : 26 2 esp_usb_jtag.c:891 esp_usb_jtag_vid_pid(): esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Debug: 27 2 command.c:152 script_debug(): command - espusbjtag caps_descriptor 0x2000
Info : 28 2 esp_usb_jtag.c:902 esp_usb_jtag_caps_descriptor(): esp_usb_jtag: capabilities descriptor set to 0x2000
Debug: 29 2 command.c:152 script_debug(): command - adapter speed 40000
Debug: 30 2 adapter.c:262 adapter_config_khz(): handle adapter khz
Debug: 31 2 adapter.c:226 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 32 2 adapter.c:226 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 33 2 command.c:152 script_debug(): command - ocd_find target/esp32c3.cfg
Debug: 34 2 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/target/esp32c3.cfg

Debug: 35 2 command.c:152 script_debug(): command - ocd_find target/esp_common.cfg
Debug: 36 2 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/target/esp_common.cfg

Debug: 37 3 command.c:152 script_debug(): command - ocd_find bitsbytes.tcl
Debug: 38 3 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/bitsbytes.tcl

Debug: 39 3 command.c:152 script_debug(): command - ocd_find memory.tcl

Debug: 40 3 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/memory.tcl

Debug: 41 4 command.c:152 script_debug(): command - ocd_find mmr_helpers.tcl
Debug: 42 4 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/mmr_helpers.tcl

Debug: 43 4 command.c:152 script_debug(): command - ocd_find target/esp_version.cfg
Debug: 44 4 configuration.c:88 find_file(): found /Users/shuhao/.espressif/tools/openocd-esp32/v0.12.0-esp32-20241016/openocd-esp32/share/openocd/scripts/target/esp_version.cfg

Debug: 45 4 command.c:152 script_debug(): command - version
Debug: 46 4 command.c:152 script_debug(): command - add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock and encrypt are optional
Debug: 47 4 command.c:152 script_debug(): command - add_usage_text program_esp <filename> [address] [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock] [encrypt]
Debug: 48 4 command.c:152 script_debug(): command - add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project
Debug: 49 4 command.c:152 script_debug(): command - add_usage_text program_esp_bins <build_dir> flasher_args.json [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock]
Debug: 50 4 command.c:152 script_debug(): command - add_help_text esp_get_mac Print MAC address of the chip. Use a `format` argument to return formatted MAC value
Debug: 51 4 command.c:152 script_debug(): command - add_usage_text esp_get_mac [format]
Debug: 52 4 command.c:152 script_debug(): command - jtag newtap esp32c3 tap0 -irlen 5 -expected-id 0x00005c25
Debug: 53 4 tcl.c:405 handle_jtag_newtap_args(): Creating New Tap, Chip: esp32c3, Tap: tap0, Dotted: esp32c3.tap0, 4 params
Debug: 54 4 core.c:1477 jtag_tap_init(): Created Tap: esp32c3.tap0 @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 55 4 command.c:152 script_debug(): command - target create esp32c3 esp32c3 -chain-position esp32c3.tap0 -coreid 0 -rtos FreeRTOS
Debug: 56 4 target.c:2139 target_free_all_working_areas_restore(): freeing all working areas
Debug: 57 4 FreeRTOS.c:1472 freertos_create(): freertos_create
Debug: 58 4 command.c:258 register_command(): command 'esp' is already registered

Debug: 59 4 command.c:258 register_command(): command 'esp32c3 esp' is already registered
Debug: 60 4 command.c:152 script_debug(): command - esp32c3 configure -work-area-phys 0x3FC80000 -work-area-virt 0x3FC80000 -work-area-size 0x24000 -work-area-backup 1
Debug: 61 4 target.c:2139 target_free_all_working_areas_restore(): freeing all working areas
Debug: 62 4 target.c:2139 target_free_all_working_areas_restore(): freeing all working areas
Debug: 63 4 target.c:2139 target_free_all_working_areas_restore(): freeing all working areas
Debug: 64 4 target.c:2139 target_free_all_working_areas_restore(): freeing all working areas
Debug: 65 4 command.c:152 script_debug(): command - flash bank esp32c3.flash esp32c3 0x0 0 0 0 esp32c3
Debug: 66 4 command.c:258 register_command(): command 'esp' is already registered
Debug: 67 4 tcl.c:1308 handle_flash_bank_command(): 'esp32c3' driver usage field missing

Debug: 68 4 command.c:152 script_debug(): command - flash bank esp32c3.irom esp32c3 0x0 0 0 0 esp32c3
Debug: 69 4 command.c:258 register_command(): command 'esp' is already registered
Debug: 70 4 command.c:258 register_command(): command 'esp appimage_offset' is already registered
Debug: 71 4 command.c:258 register_command(): command 'esp compression' is already registered
Debug: 72 4 command.c:258 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 73 4 command.c:258 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 74 4 command.c:258 register_command(): command 'esp encrypt_binary' is already registered
Debug: 75 4 command.c:258 register_command(): command 'esp stub_log' is already registered
Debug: 76 4 tcl.c:1308 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 77 4 command.c:152 script_debug(): command - flash bank esp32c3.drom esp32c3 0x0 0 0 0 esp32c3
Debug: 78 4 command.c:258 register_command(): command 'esp' is already registered
Debug: 79 4 command.c:258 register_command(): command 'esp appimage_offset' is already registered
Debug: 80 4 command.c:258 register_command(): command 'esp compression' is already registered
Debug: 81 4 command.c:258 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 82 4 command.c:258 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 83 4 command.c:258 register_command(): command 'esp encrypt_binary' is already registered
Debug: 84 4 command.c:258 register_command(): command 'esp stub_log' is already registered
Debug: 85 4 tcl.c:1308 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 86 5 command.c:152 script_debug(): command - esp32c3 configure -event halted 
		global _ESP_WDT_DISABLE
		$_ESP_WDT_DISABLE
		esp halted_event_handler
	
Debug: 87 5 command.c:152 script_debug(): command - esp32c3 configure -event examine-end 
		# Need to enable to set 'semihosting_basedir'
		arm semihosting enable
		arm semihosting_resexit enable
		if { [info exists _SEMIHOST_BASEDIR] } {
			if { $_SEMIHOST_BASEDIR != "" } {
				arm semihosting_basedir $_SEMIHOST_BASEDIR
			}
		}
	
Debug: 88 5 command.c:152 script_debug(): command - esp32c3 configure -event reset-assert-post 
		global _ESP_SOC_RESET
		$_ESP_SOC_RESET
	
Debug: 89 5 command.c:152 script_debug(): command - esp32c3 configure -event gdb-attach 
		if { $_ESP_ARCH == "xtensa" } {
			$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
		}
		# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
		halt 1000
		if { [$_ESP_MEMPROT_IS_ENABLED] } {
			# 'reset halt' to disable memory protection and allow flasher to work correctly
			echo "Memory protection is enabled. Reset target to disable it..."
			reset halt
		}

		if { $_ESP_ARCH == "riscv" } {
			# by default mask interrupts while stepping
			$_TARGETNAME_0 riscv set_maskisr steponly
		}
	
Debug: 90 5 command.c:152 script_debug(): command - riscv set_reset_timeout_sec 2
Debug: 91 5 command.c:152 script_debug(): command - riscv set_command_timeout_sec 5
Debug: 92 5 command.c:152 script_debug(): command - esp32c3 riscv set_mem_access sysbus progbuf abstract
Debug: 93 5 command.c:152 script_debug(): command - esp32c3 riscv set_ebreakm on
Debug: 94 5 command.c:152 script_debug(): command - esp32c3 riscv set_ebreaks on
Debug: 95 5 command.c:152 script_debug(): command - esp32c3 riscv set_ebreaku on
Debug: 96 5 command.c:152 script_debug(): command - esp32c3 riscv expose_csrs 2016=mpcer
Debug: 97 5 command.c:152 script_debug(): command - esp32c3 riscv expose_csrs 2017=mpcmr
Debug: 98 5 command.c:152 script_debug(): command - esp32c3 riscv expose_csrs 2018=mpccr
Debug: 99 5 command.c:152 script_debug(): command - esp32c3 riscv expose_csrs 2051=cpu_gpio_oen
Debug: 100 5 command.c:152 script_debug(): command - esp32c3 riscv expose_csrs 2052=cpu_gpio_in
Debug: 101 5 command.c:152 script_debug(): command - esp32c3 riscv expose_csrs 2053=cpu_gpio_out

Info : 102 5 server.c:299 add_service(): Listening on port 6666 for tcl connections
Info : 103 5 server.c:299 add_service(): Listening on port 4444 for telnet connections
Debug: 104 5 command.c:152 script_debug(): command - init
Debug: 105 5 command.c:152 script_debug(): command - target init
Debug: 106 5 command.c:152 script_debug(): command - target names
Debug: 107 5 command.c:152 script_debug(): command - esp32c3 cget -event gdb-flash-erase-start
Debug: 108 5 command.c:152 script_debug(): command - esp32c3 configure -event gdb-flash-erase-start reset init
Debug: 109 5 command.c:152 script_debug(): command - esp32c3 cget -event gdb-flash-write-end
Debug: 110 5 command.c:152 script_debug(): command - esp32c3 configure -event gdb-flash-write-end reset halt
Debug: 111 5 command.c:152 script_debug(): command - esp32c3 cget -event gdb-attach
Debug: 112 5 target.c:1597 handle_target_init_command(): Initializing targets...
Debug: 113 5 riscv.c:449 riscv_init_target(): [esp32c3] riscv_init_target()
Debug: 114 5 semihosting_common.c:105 semihosting_common_init():  

Info : 115 11 esp_usb_jtag.c:651 esp_usb_jtag_init(): esp_usb_jtag: serial (24:58:7C:AC:B8:8C)

Debug: 116 11 libusb_helper.c:441 jtag_libusb_choose_interface(): usb ep out 02
Debug: 117 11 libusb_helper.c:441 jtag_libusb_choose_interface(): usb ep in 83
Debug: 118 11 libusb_helper.c:449 jtag_libusb_choose_interface(): Claiming interface 2

Info : 119 14 esp_usb_jtag.c:728 esp_usb_jtag_init(): esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255

Debug: 120 16 adapter.c:226 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 121 16 adapter.c:230 adapter_khz_to_speed(): have adapter set up
Debug: 122 16 esp_usb_jtag.c:788 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1
Debug: 123 16 esp_usb_jtag.c:804 esp_usb_jtag_speed(): esp_usb_jtag: setting divisor 1

Debug: 124 18 adapter.c:226 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 125 18 adapter.c:230 adapter_khz_to_speed(): have adapter set up
Debug: 126 18 esp_usb_jtag.c:788 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1
Info : 127 18 adapter.c:190 adapter_init(): clock speed 40000 kHz
Debug: 128 18 openocd.c:133 handle_init_command(): Debug Adapter init complete

Debug: 129 18 command.c:152 script_debug(): command - transport init
Debug: 130 18 transport.c:218 handle_transport_init(): handle_transport_init
Debug: 131 18 core.c:716 legacy_jtag_add_reset(): SRST line released
Debug: 132 18 core.c:740 legacy_jtag_add_reset(): TRST line released
Debug: 133 18 core.c:326 jtag_call_event_callbacks(): jtag event: TAP reset

Debug: 134 18 command.c:152 script_debug(): command - jtag arp_init
Debug: 135 18 core.c:1508 jtag_init_inner(): Init JTAG chain
Debug: 136 18 core.c:326 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 137 19 core.c:1233 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 138 19 core.c:326 jtag_call_event_callbacks(): jtag event: TAP reset

Info : 139 19 core.c:1131 jtag_examine_chain_display(): JTAG tap: esp32c3.tap0 tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)
Debug: 140 19 core.c:1363 jtag_validate_ircapture(): IR capture validation scan

Debug: 141 19 core.c:1421 jtag_validate_ircapture(): esp32c3.tap0: IR capture 0x05

Debug: 142 20 command.c:152 script_debug(): command - dap init
Debug: 143 20 arm_dap.c:95 dap_init_all(): Initializing all DAPs ...
Debug: 144 20 openocd.c:150 handle_init_command(): Examining targets...
Debug: 145 20 target.c:683 target_examine_one(): [esp32c3] Examination started
Debug: 146 20 target.c:1785 target_call_event_callbacks(): target event 19 (examine-start) for core esp32c3
Debug: 147 20 riscv.c:1722 riscv_examine(): [esp32c3] Starting examination

Debug: 148 20 riscv.c:405 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 149 20 riscv.c:1736 riscv_examine(): [esp32c3] dtmcontrol=0x1071
Debug: 150 20 riscv.c:1738 riscv_examine(): [esp32c3] version=0x1
Debug: 151 20 riscv-013.c:2784 init_target(): [esp32c3] Init.
Debug: 152 20 riscv-013.c:1897 examine(): [esp32c3] dbgbase=0x0

Debug: 153 20 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 154 20 riscv-013.c:1905 examine(): [esp32c3] dtmcontrol=0x1071

Debug: 155 20 riscv-013.c:1906 examine(): [esp32c3] dtmcs=0x1071 {version=1_0 idle=1 errinfo=not_implemented abits=7}
Debug: 156 20 riscv-013.c:768 check_dbgbase_exists(): [esp32c3] Searching for DM with DMI base address (dbgbase) = 0x0
Debug: 157 20 riscv-013.c:251 get_dm(): [esp32c3] Coreid [0] Allocating new DM
Debug: 158 20 riscv-013.c:495 dmi_scan(): [esp32c3] reset_delays_wait done

Debug: 159 21 riscv-013.c:466 increase_dmi_busy_delay(): [esp32c3] dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0

Debug: 160 22 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71

Debug: 161 22 riscv-013.c:5185 riscv013_invalidate_cached_progbuf(): [esp32c3] Invalidating progbuf cache

Debug: 162 23 riscv-013.c:466 increase_dmi_busy_delay(): [esp32c3] dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0

Debug: 163 23 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071

Debug: 164 24 riscv-013.c:1979 examine(): [esp32c3] dmstatus:  0x000c0ca2
Debug: 165 24 riscv-013.c:1995 examine(): [esp32c3] hartsellen=20

Info : 166 26 riscv-013.c:2023 examine(): [esp32c3] datacount=2 progbufsize=16

Debug: 167 27 riscv-013.c:2060 examine(): [esp32c3] Detected 1 harts.

Debug: 168 28 riscv-013.c:4960 select_prepped_harts(): [esp32c3] index=0, prepped=1
Debug: 169 28 riscv-013.c:5014 riscv013_halt_go(): [esp32c3] halting hart

Debug: 170 29 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x321008 {regno=0x1008 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=64bit}

Debug: 171 30 riscv-013.c:917 execute_abstract_command(): [esp32c3] command 0x321008 failed; abstractcs=0x10000202

Debug: 172 30 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x221008 {regno=0x1008 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 173 32 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x221009 {regno=0x1009 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 174 33 riscv-013.c:1720 register_read_direct(): [esp32c3] Reading misa
Debug: 175 33 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x220301 {regno=0x301 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 176 34 riscv-013.c:1740 register_read_direct(): [esp32c3] misa = 0x40101104
Debug: 177 34 riscv-013.c:1720 register_read_direct(): [esp32c3] Reading vlenb
Debug: 178 34 riscv-013.c:1225 prep_for_register_access(): [esp32c3] Preparing mstatus to access vlenb
Debug: 179 34 riscv.c:5278 riscv_get_register(): [esp32c3] No cache, reading mstatus from target
Debug: 180 34 riscv-013.c:4889 riscv013_get_register(): [esp32c3] reading register mstatus

Debug: 181 34 riscv-013.c:1720 register_read_direct(): [esp32c3] Reading mstatus
Debug: 182 34 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x220300 {regno=0x300 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 183 35 riscv-013.c:1740 register_read_direct(): [esp32c3] mstatus = 0x89
Debug: 184 35 riscv.c:5183 riscv_set_or_write_register(): [esp32c3] No cache, writing to target: mstatus <- 0x289
Debug: 185 35 riscv-013.c:4906 riscv013_set_register(): [esp32c3] writing 0x289 to register mstatus
Debug: 186 35 riscv-013.c:1692 register_write_direct(): [esp32c3] Writing 0x289 to mstatus

Debug: 187 36 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x230300 {regno=0x300 write=register transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 188 36 riscv-013.c:1711 register_write_direct(): [esp32c3] mstatus <- 0x289
Debug: 189 36 riscv-013.c:1245 prep_for_register_access(): [esp32c3] Prepared to access vlenb (mstatus=0x289)
Debug: 190 36 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x220c22 {regno=0xc22 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 191 37 riscv-013.c:917 execute_abstract_command(): [esp32c3] command 0x220c22 failed; abstractcs=0x10000302

Debug: 192 37 program.c:38 riscv_program_write(): [esp32c3] progbuf[00] = DASM(0xc2202473)

Debug: 193 38 program.c:38 riscv_program_write(): [esp32c3] progbuf[01] = DASM(0x00100073)

Debug: 194 38 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x241000 {regno=0x1000 write=arg0 transfer=disabled postexec=enabled aarpostincrement=disabled aarsize=32bit}

Debug: 195 39 riscv-013.c:917 execute_abstract_command(): [esp32c3] command 0x241000 failed; abstractcs=0x10000302

Debug: 196 39 program.c:78 riscv_program_exec(): [esp32c3] Unable to execute program 0x16f2ca0b0
Debug: 197 39 riscv-013.c:1256 cleanup_after_register_access(): [esp32c3] Restoring mstatus to 0x89
Debug: 198 39 riscv.c:5183 riscv_set_or_write_register(): [esp32c3] No cache, writing to target: mstatus <- 0x89
Debug: 199 39 riscv-013.c:4906 riscv013_set_register(): [esp32c3] writing 0x89 to register mstatus
Debug: 200 39 riscv-013.c:1692 register_write_direct(): [esp32c3] Writing 0x89 to mstatus

Debug: 201 40 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x230300 {regno=0x300 write=register transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 202 41 riscv-013.c:1711 register_write_direct(): [esp32c3] mstatus <- 0x89
Debug: 203 41 riscv-013.c:1720 register_read_direct(): [esp32c3] Reading mtopi
Debug: 204 41 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x220fb0 {regno=0xfb0 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 205 42 riscv-013.c:917 execute_abstract_command(): [esp32c3] command 0x220fb0 failed; abstractcs=0x10000302

Debug: 206 42 program.c:38 riscv_program_write(): [esp32c3] progbuf[00] = DASM(0xfb002473)

Debug: 207 43 program.c:38 riscv_program_write(): [esp32c3] progbuf[01] = DASM(0x00100073)
Debug: 208 43 riscv-013.c:5163 riscv013_write_progbuf(): [esp32c3] Cache hit for 0x100073 @1

Debug: 209 43 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x241000 {regno=0x1000 write=arg0 transfer=disabled postexec=enabled aarpostincrement=disabled aarsize=32bit}

Debug: 210 44 riscv-013.c:917 execute_abstract_command(): [esp32c3] command 0x241000 failed; abstractcs=0x10000302

Debug: 211 44 program.c:78 riscv_program_exec(): [esp32c3] Unable to execute program 0x16f2ca0b0
Debug: 212 44 riscv-013.c:2144 examine(): [esp32c3]  XLEN=32, misa=0x40101104
Debug: 213 44 riscv-013.c:1692 register_write_direct(): [esp32c3] Writing 0x8 to fp

Debug: 214 45 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x231008 {regno=0x1008 write=register transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 215 46 riscv-013.c:1711 register_write_direct(): [esp32c3] fp <- 0x8
Debug: 216 46 riscv-013.c:1692 register_write_direct(): [esp32c3] Writing 0x1 to s1

Debug: 217 46 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x231009 {regno=0x1009 write=register transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 218 47 riscv-013.c:1711 register_write_direct(): [esp32c3] s1 <- 0x1
Debug: 219 47 riscv.c:5891 riscv_init_registers(): [esp32c3] create register cache for 4194 registers

Debug: 220 47 riscv.c:6290 riscv_init_registers(): [esp32c3] Exposing additional CSR 2016 (name=csr_mpcer)
Debug: 221 47 riscv.c:6290 riscv_init_registers(): [esp32c3] Exposing additional CSR 2017 (name=csr_mpcmr)
Debug: 222 47 riscv.c:6290 riscv_init_registers(): [esp32c3] Exposing additional CSR 2018 (name=csr_mpccr)

Debug: 223 47 riscv.c:6290 riscv_init_registers(): [esp32c3] Exposing additional CSR 2051 (name=csr_cpu_gpio_oen)
Debug: 224 47 riscv.c:6290 riscv_init_registers(): [esp32c3] Exposing additional CSR 2052 (name=csr_cpu_gpio_in)
Debug: 225 47 riscv.c:6290 riscv_init_registers(): [esp32c3] Exposing additional CSR 2053 (name=csr_cpu_gpio_out)

Debug: 226 48 riscv-013.c:1770 set_dcsr_ebreak(): [esp32c3] Set dcsr.ebreak*
Debug: 227 48 riscv.c:5295 riscv_get_register(): [esp32c3] Reading dcsr from target
Debug: 228 48 riscv-013.c:4889 riscv013_get_register(): [esp32c3] reading register dcsr
Debug: 229 48 riscv-013.c:1720 register_read_direct(): [esp32c3] Reading dcsr

Debug: 230 48 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x2207b0 {regno=0x7b0 write=arg0 transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 231 49 riscv-013.c:1740 register_read_direct(): [esp32c3] dcsr = 0xc3
Debug: 232 49 riscv.c:5303 riscv_get_register(): [esp32c3] Read dcsr: 0xc3
Debug: 233 49 riscv.c:5210 riscv_set_or_write_register(): [esp32c3] Writing to target: dcsr <- 0x90c3 (cacheable=false, valid=true, dirty=false)
Debug: 234 49 riscv-013.c:4906 riscv013_set_register(): [esp32c3] writing 0x90c3 to register dcsr
Debug: 235 49 riscv-013.c:1692 register_write_direct(): [esp32c3] Writing 0x90c3 to dcsr

Debug: 236 49 riscv-013.c:893 execute_abstract_command(): [esp32c3] access register=0x2307b0 {regno=0x7b0 write=register transfer=enabled postexec=disabled aarpostincrement=disabled aarsize=32bit}

Debug: 237 49 riscv-013.c:1711 register_write_direct(): [esp32c3] dcsr <- 0x90c3
Debug: 238 49 riscv.c:5226 riscv_set_or_write_register(): [esp32c3] Wrote 0x90c3 to dcsr (cacheable=false, valid=false, dirty=false)
Debug: 239 49 riscv-013.c:5281 riscv013_step_or_resume_current_hart(): [esp32c3] resuming (for step?=0)

Info : 240 51 riscv-013.c:2187 examine(): [esp32c3] Examined RISC-V core; found 1 harts
Info : 241 51 riscv-013.c:2188 examine(): [esp32c3]  XLEN=32, misa=0x40101104

Debug: 242 51 target.c:1785 target_call_event_callbacks(): target event 21 (examine-end) for core esp32c3
Debug: 243 51 target.c:4690 target_handle_event(): target: esp32c3 (esp32c3) event: 21 (examine-end) action: 
		# Need to enable to set 'semihosting_basedir'
		arm semihosting enable
		arm semihosting_resexit enable
		if { [info exists _SEMIHOST_BASEDIR] } {
			if { $_SEMIHOST_BASEDIR != "" } {
				arm semihosting_basedir $_SEMIHOST_BASEDIR
			}
		}
	
Debug: 244 51 command.c:152 script_debug(): command - arm semihosting enable

Debug: 245 51 riscv_semihosting.c:169 riscv_semihosting_setup(): [esp32c3] enable=1
Debug: 246 51 command.c:152 script_debug(): command - arm semihosting_resexit enable

Debug: 247 51 command.c:152 script_debug(): command - arm semihosting_basedir .
Info : 248 51 target.c:699 target_examine_one(): [esp32c3] Examination succeed
Debug: 249 51 command.c:152 script_debug(): command - flash init
Debug: 250 51 tcl.c:1365 handle_flash_init_command(): Initializing flash devices...

Debug: 251 51 command.c:152 script_debug(): command - nand init
Debug: 252 51 tcl.c:484 handle_nand_init_command(): Initializing NAND devices...
Debug: 253 51 command.c:152 script_debug(): command - pld init
Debug: 254 51 pld.c:337 handle_pld_init_command(): Initializing PLDs...
Debug: 255 51 command.c:152 script_debug(): command - tpiu init
Info : 256 51 gdb_server.c:3854 gdb_target_start(): [esp32c3] starting gdb server on 3333

Info : 257 51 server.c:299 add_service(): Listening on port 3333 for gdb connections
Debug: 258 51 command.c:152 script_debug(): command - target names

Debug: 259 52 command.c:152 script_debug(): command - target names
Debug: 260 52 command.c:152 script_debug(): command - esp32c3 cget -type

[erhankur]

@Shu244 Thanks for the log but I don't see any error. What happens when you start debugging? What is the error you get?
Did you add a breakpoint to the app_main and try to step from there? Please share more details so that we can help you.

[Shu244]

@erhankur yes I have a break point set, the debugger simply never starts:

[erhankur]

And any logs in the termninal/ debug console?

@brianignacio5 could you please help?

[Shu244]

@erhankur the debug console had this log:

GNU gdb (esp-gdb) 14.2_20240403
Copyright (C) 2023 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=aarch64-apple-darwin21.1 --target=riscv32-esp-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
    <http://www.gnu.org/software/gdb/documentation/>.

For help, type "help".
Type "apropos word" to search for commands related to "word".
dyld[5102]: missing symbol called


Fatal signal: Abort trap: 6
----- Backtrace -----
Backtrace unavailable
---------------------
A fatal error internal to GDB has been detected, further
debugging is not possible.  GDB will now terminate.

This is a bug, please report it.  For instructions, see:
<https://www.gnu.org/software/gdb/bugs/>.

[erhankur]

From one terminal

cd hello_world
idf.py set-target esp32c3
idf.py flash
idf.py openocd

From the other terminal

idf.py gdb
# idf.py gdbgui or idf.py gdbtui depends on your choice

Please try debugging it this way. I wonder if you will still see a GDB error.

I don't know the exact reason yet but seems you are not alone. https://stackoverflow.com/questions/78855046/esp32-gdb-debugging-error-on-m1-mac-dyld-missing-symbol-called