·
67 commits
to master
since this release
Features:
- flash: Added esp32c61 flash support.
- target/esp32c5: Added reset reason logging.
- target/esp32c61: Added reset reason logging.
- target/esp32p4: Added TCM memory as a valid memory region.
- target/espressif: Added support for printing names of extended Espressif syscalls set in the log.
Bug fixes:
- target/riscv: Call target reset handler for also resets initiated outside of OpenOCD. Previously it was called only for resets initiated by OpenOCD itself.
Therefore reset reasons were not printed when target is reset by HW signal or via SW reset initiated due to the panic. - target/esp32p4: Invalidate L1 ICache after writing the memory to fix the SW breakpoint miss issue.
- target/esp_riscv: Halt other cores before running bp/wp set commands. Could lead to missing bp/wp hits by other core which were running at the moment of that semihosting call.
- target/esp_riscv: Avoid apptrace data polling during reset cycle.
- tcl/esp_riscv: Configure default riscv settings for each core. Previosuly some config options were applied to the first core only.
- target/esp_riscv: Clear WDT interrupt states when the target is halted. That could lead to spontaneous interrupt WDT panics during step/continue.
- target/esp_riscv: Avoid false floating point instruction faults which are normal and handled by panic code in IDF.
- target/esp_riscv: Filter out interrupts and report exceptions reasons only.
- tcl/esp_common: Added missing global variable in configure_esp_xtensa_default_settings TCL function.
Other:
- Synchronized with upstream.