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Rename simulator run
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ethanuppal committed Apr 22, 2024
1 parent 6bd11a7 commit 4bcf017
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Showing 4 changed files with 17 additions and 9 deletions.
2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -7,7 +7,7 @@
![CI Status](https://github.com/ethanuppal/cs3110_compiler/actions/workflows/ci.yaml/badge.svg)

> "x86 is simple trust me bro"
> Last updated: 2024-04-21 14:23:34.568195
> Last updated: 2024-04-21 21:02:46.017498
```
$ ./main -h
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9 changes: 4 additions & 5 deletions lib/ir/simulator.ml
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Expand Up @@ -5,15 +5,15 @@ type t = {

let make () = { context = Context.make (); output = "" }

let simulate simulator cfg =
let run simulator cfg =
Context.push simulator.context;
let entry = Cfg.entry cfg in
let eval = function
| Operand.Variable var ->
Context.get simulator.context (Variable.to_string var) |> Option.get
| Operand.Constant int -> int
in
let rec run bb =
let rec run_aux bb =
Basic_block.to_list bb
|> List.iter (fun ir ->
match ir with
Expand All @@ -39,11 +39,10 @@ let simulate simulator cfg =
| Conditional operand -> eval operand <> 0
in
match Cfg.take_branch cfg bb cond with
| Some bb2 -> run bb2
| Some bb2 -> run_aux bb2
| None -> ()
in

run entry
run_aux entry

let dump simulator =
Printf.sprintf "IR Simulation:\n"
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13 changes: 11 additions & 2 deletions lib/ir/simulator.mli
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@@ -1,7 +1,16 @@
(** An intermediate representation simulator. *)
(** An IR simulator. *)
type t

(** [make ()] is a new IR simulator. *)
val make : unit -> t
val simulate : t -> Cfg.t -> unit

(** [run simulator cfg] simulates [cfg] using [simulator]. *)
val run : t -> Cfg.t -> unit

(** [dump simulator] is the current variable assignments of [simulator] as a
human-readable string. *)
val dump : t -> string

(** [dump simulator] is the current standard output of [simulator] as a
human-readable string. *)
val output_of : t -> string
2 changes: 1 addition & 1 deletion test/test_snapshots.ml
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Expand Up @@ -16,7 +16,7 @@ let test_suite =
let ir = Ir_gen.generate statements in
let main_cfg = List.hd ir in
let simulator = Simulator.make () in
Simulator.simulate simulator main_cfg;
Simulator.run simulator main_cfg;
Simulator.output_of simulator)
else ""
in
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