WIP Support Kintex high speed IO banks

fuzzers/000-init-db/Makefile

@@ -50,6 +50,7 @@ DB_SIMPLE=\
  segbits_cmt_top_r_lower_b \
  segbits_rioi3 \
  segbits_riob33 \
+ segbits_riob18 \
  segbits_hclk_cmt \
  segbits_hclk_ioi3 \
 

fuzzers/001-part-yaml/generate.tcl

@@ -11,7 +11,7 @@ proc extract_iobanks {filename} {
  set sample_site [lindex [get_sites -of $iobank] 0]
  if {[llength $sample_site] == 0} continue
  set clock_region [get_property CLOCK_REGION $sample_site]
- foreach tile [get_tiles -filter {TYPE=~HCLK_IOI3}] {
+ foreach tile [concat [get_tiles -filter {TYPE=~HCLK_IOI3}] [get_tiles -filter {TYPE=~HCLK_IOI}]] {
  set tile_sites [get_sites -of_object $tile]
  if {[llength $tile_sites] == 0} continue
  set hclk_tile_clock_region [get_property CLOCK_REGION [lindex [get_sites -of_object $tile] 0]]
@@ -29,13 +29,13 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog ../../top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS18" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS18" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS18" [get_ports do]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS18" [get_ports stb]
 
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS GND [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
 set_param tcl.collectionResultDisplayLimit 0
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]

fuzzers/005-tilegrid/Makefile

@@ -49,6 +49,13 @@ endif
 
 # Kintex7 only fuzzers
 ifeq (${XRAY_DATABASE}, kintex7)
+# xc7k420t/xc7k480t have no high performance banks
+ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k480t))
+TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+endif
+
 # These kintex parts give an empty design
 ifneq (${XRAY_FABRIC}, $(filter ${XRAY_FABRIC}, xc7k160t xc7k325t xc7k480t))
 TILEGRID_TDB_DEPENDENCIES += orphan_int_column/$(BUILD_FOLDER)/segbits_tilegrid.tdb
@@ -85,12 +92,21 @@ cfg/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 iob/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
  cd iob && $(MAKE)
 
+iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+ cd iob18 && $(MAKE)
+
 iob_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
  cd iob_int && $(MAKE)
 
+iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+ cd iob18_int && $(MAKE)
+
 ioi/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
  cd ioi && $(MAKE)
 
+ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+ cd ioi18 && $(MAKE)
+
 mmcm/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
  cd mmcm && $(MAKE)
 
@@ -177,8 +193,11 @@ clean:
  cd clb_int && $(MAKE) clean
  cd cfg && $(MAKE) clean
  cd iob && $(MAKE) clean
+ cd iob18 && $(MAKE) clean
  cd iob_int && $(MAKE) clean
+ cd iob18_int && $(MAKE) clean
  cd ioi && $(MAKE) clean
+ cd ioi18 && $(MAKE) clean
  cd mmcm && $(MAKE) clean
  cd pll && $(MAKE) clean
  cd ps7_int && $(MAKE) clean
@@ -208,8 +227,11 @@ clean_part:
  cd clb_int && $(MAKE) clean_part
  cd cfg && $(MAKE) clean_part
  cd iob && $(MAKE) clean_part
+ cd iob18 && $(MAKE) clean_part
  cd iob_int && $(MAKE) clean_part
+ cd iob18_int && $(MAKE) clean_part
  cd ioi && $(MAKE) clean_part
+ cd ioi18 && $(MAKE) clean_part
  cd mmcm && $(MAKE) clean_part
  cd pll && $(MAKE) clean_part
  cd ps7_int && $(MAKE) clean_part

fuzzers/005-tilegrid/add_tdb.py

@@ -94,7 +94,9 @@ def run(fn_in, fn_out, verbose=False):
  int_frames, int_words = localutil.get_int_params()
  tdb_fns = [
  ("iob", 42, 4),
+ ("iob18", 42, 4),
  ("ioi", 42, 4),
+ ("ioi18", 42, 4),
  ("mmcm", 30, 49),
  ("pll", 30, 27),
  ("monitor", 30, 101),
@@ -112,6 +114,7 @@ def run(fn_in, fn_out, verbose=False):
  ("gtp_channel", 32, 22),
  ("clb_int", int_frames, int_words),
  ("iob_int", int_frames, int_words),
+ ("iob18_int", int_frames, int_words),
  ("bram_int", int_frames, int_words),
  ("dsp_int", int_frames, int_words),
  ("fifo_int", int_frames, int_words),

fuzzers/005-tilegrid/generate_full.py

@@ -369,7 +369,7 @@ def propagate_IOB_SING(database, tiles_by_grid):
  if tile in seen_iobs:
  continue
 
- if database[tile]["type"] not in ["LIOB33", "RIOB33"]:
+ if database[tile]["type"] not in ["LIOB33", "RIOB33", "RIOB18"]:
  continue
 
  while True:
@@ -439,7 +439,7 @@ def propagate_IOI_SING(database, tiles_by_grid):
  if tile in seen_iois:
  continue
 
- if database[tile]["type"] not in ["LIOI3", "RIOI3"]:
+ if database[tile]["type"] not in ["LIOI3", "RIOI3", "RIOI"]:
  continue
 
  while True:

fuzzers/005-tilegrid/iob18/Makefile

@@ -0,0 +1,10 @@
+# Copyright (C) 2017-2020 The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 30
+GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 26 --dword 0"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/iob18/generate.tcl

@@ -0,0 +1,86 @@
+# Copyright (C) 2017-2020 The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc make_io_pin_sites {} {
+ # get all possible IOB pins
+ foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
+ set site [get_sites -of_objects $pad]
+ if {[llength $site] == 0} {
+ continue
+ }
+ if [string match IOB18* [get_property SITE_TYPE $site]] {
+ dict append io_pin_sites $site $pad
+ }
+ }
+ return $io_pin_sites
+}
+
+proc load_pin_lines {} {
+ # IOB_X0Y103 clk input
+ # IOB_X0Y129 do[0] output
+
+ set fp [open "params.csv" r]
+ gets $fp line
+
+ set pin_lines {}
+ for {gets $fp line} {$line != ""} {gets $fp line} {
+ lappend pin_lines [split $line ","]
+ }
+ close $fp
+ return $pin_lines
+}
+
+proc loc_pins {} {
+ set pin_lines [load_pin_lines]
+ set io_pin_sites [make_io_pin_sites]
+
+ puts "Looping"
+ for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
+ set line [lindex $pin_lines $idx]
+ puts "$line"
+
+ set site_str [lindex $line 2]
+ set pin_str [lindex $line 3]
+
+ # Have: site
+ # Want: pin for site
+
+ set site [get_sites $site_str]
+ set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
+ # set port [get_ports -of_objects $site]
+ set port [get_ports $pin_str]
+ set tile [get_tiles -of_objects $site]
+
+ set pin [dict get $io_pin_sites $site]
+ set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS18" $port
+ }
+}
+
+proc run {} {
+ create_project -force -part $::env(XRAY_PART) design design
+ read_verilog top.v
+ synth_design -top top
+
+ loc_pins
+
+ set_property CFGBVS GND [current_design]
+ set_property CONFIG_VOLTAGE 1.8 [current_design]
+ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+ set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
+ set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+ set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+
+ place_design
+ route_design
+
+ write_checkpoint -force design.dcp
+ write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/iob18/top.py

@@ -0,0 +1,84 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020 The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+ '''
+ IOB18S: main IOB of a diff pair
+ IOB18M: secondary IOB of a diff pair
+ IOB18: not a diff pair. Relatively rare (at least in ROI...2 of them?)
+ Focus on IOB18S to start
+ '''
+ db = Database(util.get_db_root(), util.get_part())
+ grid = db.grid()
+ for tile_name in sorted(grid.tiles()):
+ loc = grid.loc_of_tilename(tile_name)
+ gridinfo = grid.gridinfo_at_loc(loc)
+
+ for site_name, site_type in gridinfo.sites.items():
+ if site_type == 'IOB18S':
+ yield tile_name, site_name
+
+
+def write_params(params):
+ pinstr = 'tile,val,site,pin\n'
+ for tile, (site, val, pin) in sorted(params.items()):
+ pinstr += '%s,%s,%s,%s\n' % (tile, val, site, pin)
+ open('params.csv', 'w').write(pinstr)
+
+
+def run():
+ sites = list(gen_sites())
+ print(
+ '''
+`define N_DI {}
+
+module top(input wire [`N_DI-1:0] di);
+ wire [`N_DI-1:0] di_buf;
+ '''.format(len(sites)))
+
+ params = {}
+ print('''
+ (* KEEP, DONT_TOUCH *)
+ LUT6 dummy_lut();''')
+
+ for idx, ((tile_name, site_name), isone) in enumerate(zip(
+ sites, util.gen_fuzz_states(len(sites)))):
+ params[tile_name] = (site_name, isone, "di[%u]" % idx)
+ print(
+ '''
+ (* KEEP, DONT_TOUCH *)
+ IBUF #(
+ ) ibuf_{site_name} (
+ .I(di[{idx}]),
+ .O(di_buf[{idx}])
+ );'''.format(site_name=site_name, idx=idx))
+
+ if isone:
+ print(
+ '''
+ (* KEEP, DONT_TOUCH *)
+ PULLUP #(
+ ) pullup_{site_name} (
+ .O(di[{idx}])
+ );'''.format(site_name=site_name, idx=idx))
+
+ print("endmodule")
+ write_params(params)
+
+
+if __name__ == '__main__':
+ run()

fuzzers/005-tilegrid/iob18_int/Makefile

@@ -0,0 +1,10 @@
+# Copyright (C) 2017-2020 The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 16
+GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 14 --dword 1"
+include ../fuzzaddr/common.mk