Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Bump to scala 2.13/chisel 3.5.5/latest rocketchip #36

Merged
merged 1 commit into from
Feb 1, 2023
Merged

Bump to scala 2.13/chisel 3.5.5/latest rocketchip #36

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion build.sbt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,4 @@ version := "1.0"

name := "icenet"

scalaVersion := "2.12.10"
scalaVersion := "2.13.10"
9 changes: 6 additions & 3 deletions src/main/scala/DMA.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,8 @@ class StreamReader(nXacts: Int, outFlits: Int, maxBytes: Int)
val core = LazyModule(new StreamReaderCore(nXacts, outFlits, maxBytes))
val node = core.node

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val dataBits = core.module.dataBits

val io = IO(new Bundle {
Expand All @@ -46,7 +47,8 @@ class StreamReaderCore(nXacts: Int, outFlits: Int, maxBytes: Int)
val node = TLHelper.makeClientNode(
name = "stream-reader", sourceId = IdRange(0, nXacts))

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (tl, edge) = node.out(0)
val dataBits = tl.params.dataBits
val beatBytes = dataBits / 8
Expand Down Expand Up @@ -182,7 +184,8 @@ class StreamWriter(nXacts: Int, maxBytes: Int)
val node = TLHelper.makeClientNode(
name = "stream-writer", sourceId = IdRange(0, nXacts))

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (tl, edge) = node.out(0)
val dataBits = tl.params.dataBits
val beatBytes = dataBits / 8
Expand Down
11 changes: 7 additions & 4 deletions src/main/scala/NIC.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -179,7 +179,8 @@ class IceNicSendPath(nInputTaps: Int = 0)(implicit p: Parameters)
nMemXacts, outBufFlits, maxAcquireBytes))
val node = reader.node

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val send = Flipped(new IceNicSendIO)
val tap = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH))))
Expand Down Expand Up @@ -246,7 +247,8 @@ class IceNicWriter(implicit p: Parameters) extends NICLazyModule {
val writer = LazyModule(new StreamWriter(nMemXacts, maxAcquireBytes))
val node = writer.node

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val recv = Flipped(new IceNicRecvIO)
val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH)))
Expand Down Expand Up @@ -287,7 +289,7 @@ class IceNicRecvPath(val tapFuncs: Seq[EthernetHeader => Bool] = Nil)
lazy val module = new IceNicRecvPathModule(this)
}

class IceNicRecvPathModule(outer: IceNicRecvPath)
class IceNicRecvPathModule(val outer: IceNicRecvPath)
extends LazyModuleImp(outer) with HasNICParameters {
val io = IO(new Bundle {
val recv = Flipped(new IceNicRecvIO)
Expand Down Expand Up @@ -433,7 +435,8 @@ class IceNIC(address: BigInt, beatBytes: Int = 8,
dmanode := TLWidthWidget(NET_IF_BYTES) := sendPath.node
dmanode := TLWidthWidget(NET_IF_BYTES) := recvPath.node

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val ext = new NICIO
val tapOut = Vec(tapOutFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH)))
Expand Down
18 changes: 12 additions & 6 deletions src/main/scala/NICTests.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,8 @@ class IceNicTestSendDriver(
val node = TLHelper.makeClientNode(
name = "test-send-driver", sourceId = IdRange(0, 1))

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle with UnitTestIO {
val send = new IceNicSendIO
})
Expand Down Expand Up @@ -111,7 +112,8 @@ class IceNicTestRecvDriver(recvReqs: Seq[Int], recvData: Seq[BigInt])
val node = TLHelper.makeClientNode(
name = "test-recv-driver", sourceId = IdRange(0, 1))

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle with UnitTestIO {
val recv = new IceNicRecvIO
})
Expand Down Expand Up @@ -209,7 +211,8 @@ class IceNicRecvTest(implicit p: Parameters) extends NICLazyModule {
mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) :=
TLHelper.latency(MEM_LATENCY, xbar.node)

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle with UnitTestIO)

val gen = Module(new PacketGen(recvLens, testData))
Expand Down Expand Up @@ -260,7 +263,8 @@ class IceNicSendTest(implicit p: Parameters) extends LazyModule {
val RLIMIT_PERIOD = 0
val RLIMIT_SIZE = 8

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle with UnitTestIO)

val sendPathIO = sendPath.module.io
Expand Down Expand Up @@ -330,7 +334,8 @@ class IceNicTest(implicit p: Parameters) extends NICLazyModule {
mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) :=
TLHelper.latency(MEM_LATENCY, xbar.node)

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle with UnitTestIO)

sendPath.module.io.send <> sendDriver.module.io.send
Expand Down Expand Up @@ -478,7 +483,8 @@ class MisalignedTest(implicit p: Parameters) extends NICLazyModule {
mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) :=
TLBuffer() := xbar.node

lazy val module = new LazyModuleImp(this) {
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle with UnitTestIO)

val driver = Module(new MisalignedTestDriver)
Expand Down