Merge tag 'v5.4.282' into 5.4-main

This is the 5.4.282 stable release

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Documentation/arm64/cpu-feature-registers.rst

@@ -92,7 +92,7 @@ operation if the source belongs to the supported system register space.
 
 The infrastructure emulates only the following system register space::
 
- Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
+ Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7
 
 (See Table C5-6 'System instruction encodings for non-Debug System
 register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
@@ -167,6 +167,42 @@ infrastructure:
  | EL0 | [3-0] | n |
  +------------------------------+---------+---------+
 
+ 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FPDP | [11-8] | y |
+ +------------------------------+---------+---------+
+
+ 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | SIMDFMAC | [31-28] | y |
+ +------------------------------+---------+---------+
+ | SIMDSP | [19-16] | y |
+ +------------------------------+---------+---------+
+ | SIMDInt | [15-12] | y |
+ +------------------------------+---------+---------+
+ | SIMDLS | [11-8] | y |
+ +------------------------------+---------+---------+
+
+ 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | CRC32 | [19-16] | y |
+ +------------------------------+---------+---------+
+ | SHA2 | [15-12] | y |
+ +------------------------------+---------+---------+
+ | SHA1 | [11-8] | y |
+ +------------------------------+---------+---------+
+ | AES | [7-4] | y |
+ +------------------------------+---------+---------+
+
 
  3) MIDR_EL1 - Main ID Register
 

Documentation/arm64/silicon-errata.rst

@@ -88,12 +88,48 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM | Neoverse-N1 | #1349291 | N/A |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM | MMU-500 | #841119,826419 | N/A |
 +----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+

Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 5
 PATCHLEVEL = 4
-SUBLEVEL = 281
+SUBLEVEL = 282
 EXTRAVERSION =
 NAME = Kleptomaniac Octopus
 

arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi

@@ -259,8 +259,20 @@
 &fec {
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ phy-connection-type = "rgmii-id";
+ phy-handle = <&ethphy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1000>;
+ };
+ };
 };
 
 &i2c_intern {
@@ -500,7 +512,7 @@
  MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01  0x1b0b0 /* RST_GBE0_PHY# */
  >;
  };
 
@@ -713,7 +725,7 @@
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_pcie>;
  wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
- reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
 };
 
 /* LCD_BKLT_PWM */
@@ -801,5 +813,6 @@
  /* CPLD is feeded by watchdog (hardwired) */
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
  status = "okay";
 };

arch/arm64/Kconfig

@@ -590,6 +590,44 @@ config ARM64_ERRATUM_1742098
 
  If unsure, say Y.
 
+config ARM64_ERRATUM_3194386
+ bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
+ default y
+ help
+ This option adds the workaround for the following errata:
+
+ * ARM Cortex-A76 erratum 3324349
+ * ARM Cortex-A77 erratum 3324348
+ * ARM Cortex-A78 erratum 3324344
+ * ARM Cortex-A78C erratum 3324346
+ * ARM Cortex-A78C erratum 3324347
+ * ARM Cortex-A710 erratam 3324338
+ * ARM Cortex-A720 erratum 3456091
+ * ARM Cortex-A725 erratum 3456106
+ * ARM Cortex-X1 erratum 3324344
+ * ARM Cortex-X1C erratum 3324346
+ * ARM Cortex-X2 erratum 3324338
+ * ARM Cortex-X3 erratum 3324335
+ * ARM Cortex-X4 erratum 3194386
+ * ARM Cortex-X925 erratum 3324334
+ * ARM Neoverse-N1 erratum 3324349
+ * ARM Neoverse N2 erratum 3324339
+ * ARM Neoverse-V1 erratum 3324341
+ * ARM Neoverse V2 erratum 3324336
+ * ARM Neoverse-V3 erratum 3312417
+
+ On affected cores "MSR SSBS, #0" instructions may not affect
+ subsequent speculative instructions, which may permit unexepected
+ speculative store bypassing.
+
+ Work around this problem by placing a Speculation Barrier (SB) or
+ Instruction Synchronization Barrier (ISB) after kernel changes to
+ SSBS. The presence of the SSBS special-purpose register is hidden
+ from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
+ will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
+
+ If unsure, say Y.
+
 config CAVIUM_ERRATUM_22375
  bool "Cavium erratum 22375, 24313"
  default y

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

@@ -326,8 +326,8 @@
  <&reset RESET_HDMI_SYSTEM_RESET>,
  <&reset RESET_HDMI_TX>;
  reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
+ clocks = <&clkc CLKID_HDMI>,
+ <&clkc CLKID_HDMI_PCLK>,
  <&clkc CLKID_GCLK_VENCI_INT0>;
  clock-names = "isfr", "iahb", "venci";
 };

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

@@ -273,8 +273,8 @@
  <&reset RESET_HDMI_SYSTEM_RESET>,
  <&reset RESET_HDMI_TX>;
  reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
+ clocks = <&clkc CLKID_HDMI>,
+ <&clkc CLKID_HDMI_PCLK>,
  <&clkc CLKID_GCLK_VENCI_INT0>;
  clock-names = "isfr", "iahb", "venci";
 };

arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

@@ -302,8 +302,8 @@
  /* eMMC is shared pin with parallel NAND */
  emmc_pins_default: emmc-pins-default {
  mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
+ function = "emmc";
+ groups = "emmc", "emmc_rst";
  };
 
  /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",

arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

@@ -260,8 +260,8 @@
  /* eMMC is shared pin with parallel NAND */
  emmc_pins_default: emmc-pins-default {
  mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
+ function = "emmc";
+ groups = "emmc", "emmc_rst";
  };
 
  /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",

arch/arm64/boot/dts/qcom/msm8996.dtsi

@@ -1386,7 +1386,7 @@
  <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
  freq-table-hz =
  <100000000 200000000>,
- <0 0>,
+ <100000000 200000000>,
  <0 0>,
  <0 0>,
  <0 0>,

arch/arm64/boot/dts/qcom/sdm845.dtsi

@@ -1420,6 +1420,8 @@
  clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
  resets = <&ufs_mem_hc 0>;
  reset-names = "ufsphy";
  status = "disabled";

arch/arm64/boot/dts/rockchip/rk3328.dtsi

@@ -763,8 +763,8 @@
  <0>, <24000000>,
  <24000000>, <24000000>,
  <15000000>, <15000000>,
- <100000000>, <100000000>,
- <100000000>, <100000000>,
+ <300000000>, <100000000>,
+ <400000000>, <100000000>,
  <50000000>, <100000000>,
  <100000000>, <100000000>,
  <50000000>, <50000000>,

arch/arm64/include/asm/cpucaps.h

@@ -57,7 +57,8 @@
 #define ARM64_WORKAROUND_1542419 47
 #define ARM64_SPECTRE_BHB 48
 #define ARM64_WORKAROUND_1742098 49
+#define ARM64_WORKAROUND_SPECULATIVE_SSBS 50
 
-#define ARM64_NCAPS 50
+#define ARM64_NCAPS 51
 
 #endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cputype.h

@@ -80,6 +80,14 @@
 #define ARM_CPU_PART_CORTEX_X2 0xD48
 #define ARM_CPU_PART_NEOVERSE_N2 0xD49
 #define ARM_CPU_PART_CORTEX_A78C 0xD4B
+#define ARM_CPU_PART_CORTEX_X1C 0xD4C
+#define ARM_CPU_PART_CORTEX_X3 0xD4E
+#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
+#define ARM_CPU_PART_CORTEX_A720 0xD81
+#define ARM_CPU_PART_CORTEX_X4 0xD82
+#define ARM_CPU_PART_NEOVERSE_V3 0xD84
+#define ARM_CPU_PART_CORTEX_X925 0xD85
+#define ARM_CPU_PART_CORTEX_A725 0xD87
 
 #define APM_CPU_PART_POTENZA 0x000
 
@@ -121,6 +129,14 @@
 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
+#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
+#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
+#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
+#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
+#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
+#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
+#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

arch/arm64/kernel/cpu_errata.c

@@ -372,6 +372,19 @@ void arm64_set_ssbd_mitigation(bool state)
  asm volatile(SET_PSTATE_SSBS(0));
  else
  asm volatile(SET_PSTATE_SSBS(1));
+
+ /*
+ * SSBS is self-synchronizing and is intended to affect
+ * subsequent speculative instructions, but some CPUs can
+ * speculate with a stale value of SSBS.
+ *
+ * Mitigate this with an unconditional speculation barrier, as
+ * CPUs could mis-speculate branches and bypass a conditional
+ * barrier.
+ */
+ if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386))
+ spec_bar();
+
  return;
  }
 
@@ -828,6 +841,30 @@ static struct midr_range broken_aarch32_aes[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_ERRATUM_3194386
+static const struct midr_range erratum_spec_ssbs_list[] = {
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
+ {}
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
  {
@@ -1016,6 +1053,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
  CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
  .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
  },
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_3194386
+ {
+ .desc = "SSBS not fully self-synchronizing",
+ .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
+ ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
+ },
 #endif
  {
  }