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dts: arm64: mediatek: add MT7988A reference board device tree
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Complete device tree include for the MediaTek MT7988A SoC and make use
of it by adding the device tree of the MediaTek MT7988A Reference Board
as well as overlays for various options regarding the connected
network interfaces and storage devices present.

Available options for GMAC1 (eth0):
 * internal 4-port 1GE switch

Available options for GMAC2 (eth1):
 * internal 2.5G PHY
 * external MaxLinear 2.5G PHY
 * external Aquantia AQR113C PHY
 * SFP+ cage

Available options for GMAC3 (eth2):
 * external MaxLinear 2.5G PHY
 * external Aquantia AQR113C PHY
 * SFP+ cage

Available storage options:
 * eMMC
 * SNFI (ECC-less SPI-NAND with BCH done in SoC)
 * SPI-NAND (with ECC done by the flash die)
 * SPI-NOR
 * SD card

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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@dangowrt @frank-w
dangowrt authored and frank-w committed Sep 23, 2024
1 parent 445dd37 commit d1bc4e6
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13 changes: 13 additions & 0 deletions arch/arm64/boot/dts/mediatek/Makefile
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Expand Up @@ -47,6 +47,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nor.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-aqr.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-i2p5g-phy.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-mxl.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-sfp.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-aqr.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-mxl.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-sfp.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-snfi-nand.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nand.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nor.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
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33 changes: 33 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/

/dts-v1/;
/plugin/;

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&mmc0>;
__overlay__ {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_emmc_51>;
pinctrl-1 = <&mmc0_pins_emmc_51>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x12814>;
vqmmc-supply = <&reg_1p8v>;
vmmc-supply = <&reg_3p3v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
};
};
41 changes: 41 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;

/* external Aquantia AQR113C */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
};
};

fragment@1 {
target = <&gmac1>;
__overlay__ {
phy-mode = "usxgmii";
phy-connection-type = "usxgmii";
phy = <&phy0>;
status = "okay";
};
};
};
30 changes: 30 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&gmac1>;
__overlay__ {
phy-mode = "internal";
phy-connection-type = "internal";
phy = <&int_2p5g_phy>;
status = "okay";
};
};

fragment@1 {
target = <&int_2p5g_phy>;
__overlay__ {
pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
};
};
};
39 changes: 39 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;

/* external Maxlinear GPY211C */
phy13: ethernet-phy@13 {
reg = <13>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};

fragment@1 {
target = <&gmac1>;
__overlay__ {
phy-mode = "2500base-x";
phy-connection-type = "2500base-x";
phy = <&phy13>;
status = "okay";
};
};
};
47 changes: 47 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&i2c2>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
};

fragment@1 {
target-path = "/";
__overlay__ {
sfp_esp1: sfp@1 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
};

fragment@2 {
target = <&gmac1>;
__overlay__ {
phy-mode = "10gbase-r";
managed = "in-band-status";
sfp = <&sfp_esp1>;
status = "okay";
};
};
};
41 changes: 41 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;

/* external Aquantia AQR113C */
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
};
};

fragment@1 {
target = <&gmac2>;
__overlay__ {
phy-mode = "usxgmii";
phy-connection-type = "usxgmii";
phy = <&phy8>;
status = "okay";
};
};
};
39 changes: 39 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;

/* external Maxlinear GPY211C */
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};

fragment@1 {
target = <&gmac2>;
__overlay__ {
phy-mode = "2500base-x";
phy-connection-type = "2500base-x";
phy = <&phy5>;
status = "okay";
};
};
};
47 changes: 47 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@0 {
target = <&i2c1>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
};

fragment@1 {
target-path = "/";
__overlay__ {
sfp_esp0: sfp@0 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
};

fragment@2 {
target = <&gmac2>;
__overlay__ {
phy-mode = "10gbase-r";
managed = "in-band-status";
sfp = <&sfp_esp0>;
status = "okay";
};
};
};
31 changes: 31 additions & 0 deletions arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

/ {
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";

fragment@1 {
target-path = <&mmc0>;
__overlay__ {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_sdcard>;
pinctrl-1 = <&mmc0_pins_sdcard>;
cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
no-mmc;
status = "okay";
};
};
};
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