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4.19 hdmiv1 #51

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4.19 hdmiv1 #51

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9951d34
drm/mediatek: move dpi private data to device
May 14, 2018
3f9062c
drm/mediatek: fix to get right bridge for dpi encoder
May 14, 2018
e21d9a7
drm/mediatek: add dpi driver for mt2701 and mt7623
May 14, 2018
8a15870
drm/mediatek: add hdmi driver for different hardware
May 14, 2018
5507f54
drm/mediatek: implement connection from BLS to DPI0
BibbyHsieh May 14, 2018
ea5feec
drm/mediatek: add a error return value when clock driver has been pre…
BibbyHsieh May 14, 2018
7639877
drm/mediatek: config component output by device node port
BibbyHsieh May 14, 2018
e63def6
[hdmi] add DTS nodes
frank-w Nov 10, 2018
317e53d
[HDMI] add hdmi-options to defconfig
frank-w Nov 10, 2018
81be7d9
[HDMI] added fbdev-driver
frank-w Nov 10, 2018
4fbf8bc
[HDMI] fix compile-warnings
frank-w Nov 10, 2018
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275 changes: 275 additions & 0 deletions arch/arm/boot/dts/mt7623.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include <dt-bindings/thermal/thermal.h>

Expand All @@ -22,6 +23,11 @@
#address-cells = <2>;
#size-cells = <2>;

aliases {
rdma0 = &rdma0;
rdma1 = &rdma1;
};

cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
Expand Down Expand Up @@ -277,6 +283,17 @@
clock-names = "system-clk", "rtc-clk";
};

smi_common: smi@1000c000 {
compatible = "mediatek,mt7623-smi-common",
"mediatek,mt2701-smi-common";
reg = <0 0x1000c000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_SMI>,
<&mmsys CLK_MM_SMI_COMMON>,
<&infracfg CLK_INFRA_SMI>;
clock-names = "apb", "smi", "async";
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

pwrap: pwrap@1000d000 {
compatible = "mediatek,mt7623-pwrap",
"mediatek,mt2701-pwrap";
Expand All @@ -290,6 +307,27 @@
clock-names = "spi", "wrap";
};

mipi_tx0: mipi-dphy@10010000 {
compatible = "mediatek,mt7623-mipi-tx",
"mediatek,mt2701-mipi-tx";
reg = <0 0x10010000 0 0x90>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};

cec: cec@10012000 {
compatible = "mediatek,mt8173-cec",
"mediatek,mt7623-cec",
"mediatek,mt2701-cec";
reg = <0 0x10012000 0 0xbc>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_CEC>;
status = "disabled";
};

cir: cir@10013000 {
compatible = "mediatek,mt7623-cir";
reg = <0 0x10013000 0 0x1000>;
Expand All @@ -308,6 +346,17 @@
reg = <0 0x10200100 0 0x1c>;
};

iommu: mmsys_iommu@10205000 {
compatible = "mediatek,mt7623-m4u",
"mediatek,mt2701-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2>;
#iommu-cells = <1>;
};

efuse: efuse@10206000 {
compatible = "mediatek,mt7623-efuse",
"mediatek,mt8173-efuse";
Expand All @@ -327,6 +376,18 @@
#clock-cells = <1>;
};

hdmi_phy: phy@10209100 {
compatible = "mediatek,mt7623-hdmi-phy",
"mediatek,mt2701-hdmi-phy";
reg = <0 0x10209100 0 0x24>;
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
clock-output-names = "hdmitx_dig_cts";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};

rng: rng@1020f000 {
compatible = "mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x1000>;
Expand Down Expand Up @@ -473,6 +534,17 @@
status = "disabled";
};

hdmiddc0: i2c@11013000 {
compatible = "mediatek,mt8173-hdmi-ddc",
"mediatek,mt7623-hdmi-ddc",
"mediatek,mt2701-hdmi-ddc";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
reg = <0 0x11013000 0 0x1C>;
clocks = <&pericfg CLK_PERI_I2C3>;
clock-names = "ddc-i2c";
status = "disabled";
};

thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7623-thermal",
Expand Down Expand Up @@ -683,6 +755,201 @@
status = "disabled";
};

mmsys: syscon@14000000 {
compatible = "mediatek,mt7623-mmsys",
"mediatek,mt2701-mmsys",
"syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};

display_components: dispsys@14000000 {
compatible = "mediatek,mt7623-mmsys",
"mediatek,mt2701-mmsys";
reg = <0 0x14000000 0 0x1000>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

ovl@14007000 {
compatible = "mediatek,mt7623-disp-ovl",
"mediatek,mt2701-disp-ovl";
reg = <0 0x14007000 0 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_OVL>;
iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
mediatek,larb = <&larb0>;
};

rdma0: rdma@14008000 {
compatible = "mediatek,mt7623-disp-rdma",
"mediatek,mt2701-disp-rdma";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
mediatek,larb = <&larb0>;
};

wdma@14009000 {
compatible = "mediatek,mt7623-disp-wdma",
"mediatek,mt2701-disp-wdma";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_WDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
mediatek,larb = <&larb0>;
};

bls: bls@1400a000 {
compatible = "mediatek,mt7623-disp-pwm",
"mediatek,mt2701-disp-pwm";
reg = <0 0x1400a000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
<&mmsys CLK_MM_DISP_BLS>;
clock-names = "main", "mm";
status = "disabled";
};

color@1400b000 {
compatible = "mediatek,mt7623-disp-color",
"mediatek,mt2701-disp-color";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_COLOR>;
};

dsi: dsi@1400c000 {
compatible = "mediatek,mt7623-dsi",
"mediatek,mt2701-dsi";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DSI_ENGINE>,
<&mmsys CLK_MM_DSI_DIG>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
};

mutex: mutex@1400e000 {
compatible = "mediatek,mt7623-disp-mutex",
"mediatek,mt2701-disp-mutex";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
};

larb0: larb@14010000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x14010000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <0>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

rdma1: rdma@14012000 {
compatible = "mediatek,mt7623-disp-rdma",
"mediatek,mt2701-disp-rdma";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb0>;
};

dpi0: dpi@14014000 {
compatible = "mediatek,mt7623-dpi",
"mediatek,mt2701-dpi";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DPI1_DIGL>,
<&mmsys CLK_MM_DPI1_ENGINE>,
<&topckgen CLK_TOP_TVDPLL>;
clock-names = "pixel", "engine", "pll";
status = "disabled";
};

hdmi0: hdmi@14015000 {
compatible = "mediatek,mt8173-hdmi",
"mediatek,mt7623-hdmi",
"mediatek,mt2701-hdmi";
reg = <0 0x14015000 0 0x400>;
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
<&mmsys CLK_MM_HDMI_PLL>,
<&mmsys CLK_MM_HDMI_AUDIO>,
<&mmsys CLK_MM_HDMI_SPDIF>;
clock-names = "pixel", "pll", "bclk", "spdif";
phys = <&hdmi_phy>;
phy-names = "hdmi";
mediatek,syscon-hdmi = <&mmsys 0x900>;
cec = <&cec>;
ddc-i2c-bus = <&hdmiddc0>;
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
assigned-clock-parents = <&hdmi_phy>;
status = "disabled";
};

imgsys: syscon@15000000 {
compatible = "mediatek,mt7623-imgsys",
"mediatek,mt2701-imgsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};

larb2: larb@15001000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <2>;
clocks = <&imgsys CLK_IMG_SMI_COMM>,
<&imgsys CLK_IMG_SMI_COMM>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
};

jpegdec: jpegdec@15004000 {
compatible = "mediatek,mt7623-jpgdec",
"mediatek,mt2701-jpgdec";
reg = <0 0x15004000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};

vdecsys: syscon@16000000 {
compatible = "mediatek,mt7623-vdecsys",
"mediatek,mt2701-vdecsys",
"syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};

larb1: larb@16010000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <1>;
clocks = <&vdecsys CLK_VDEC_CKGEN>,
<&vdecsys CLK_VDEC_LARB>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
};

hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
Expand Down Expand Up @@ -924,6 +1191,14 @@
status = "disabled";
};

bdpsys: syscon@1c000000 {
compatible = "mediatek,mt7623-bdpsys",
"mediatek,mt2701-bdpsys",
"syscon";
reg = <0 0x1c000000 0 0x1000>;
#clock-cells = <1>;
};

crypto: crypto@1b240000 {
compatible = "mediatek,eip97-crypto";
reg = <0 0x1b240000 0 0x20000>;
Expand Down
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