Enable the scratch pad RAM (SPRAM)

[frno7]

The scratch pad RAM (SPRAM) of the Emotion Engine is 16 KiB of very fast static RAM organised in 128-bit quadwords. Both the DMA controller and the R5900 can access the SPRAM.

1. Can the kernel make reasonable use of the SPRAM?
2. How can a reasonable device driver interface for applications work?

[Ravenslofty]

I would use it as very fast swap space, or alternatively as part of the 3D driver; buffers of data can be DMA'd to scratchpad, and then another DMA can be set up from scratchpad to the GIF.

[FlyGoat]

https://lwn.net/Articles/536021/
Nowadays we have kernel SRAM subsystem allows us use it like DMA buffer.

[frno7]

@FlyGoat, I’m not sure the SRAM subsystem with a device tree entry or similar would work, because the scratchpad RAM in the PS2 isn’t mapped to a physical address. Instead, the MMU is 32-bit MIPS III-compatible with a special bit defined for scratchpad RAM: bit 31 of the EntryLo0 TLB register is the special S bit that indicates the memory type, where 0 means main memory and 1 means scratchpad RAM.^[1] Excerpts with additional details:

5.2.5. Scratchpad RAM Mapping
/.../
The TLB entry corresponding to SPRAM is indicated by setting the S bit to 1. The MASK field must be all zeros, and two D bits and two V bits must be the same value, respectively. The PFN and C field values are disregarded. (When read, the C field value is 2, which indicates uncached mode.)
/.../

6.4.1. SPRAM Overview
The SPRAM is similar to a tag-free Data Cache configured as 1024×128 bits. The SPRAM and the Data Cache use the same access paths, which means the CPU can access only either SPRAM or the Data Cache in any given CPU cycle. The SPRAM can be mapped into the virtual address.

SPRAM space pages are 16 KB in size. The least significant 14 bits of the virtual address indicate addresses in SPRAM. The upper 18 bits of the virtual address are used to access the TLB to determine if that particular 16 KB block is mapped into SPRAM or not. To differentiate between the memory spaces (between the Data Cache and SPRAM), the S bit in the TLB entry is used.

^[1] EE Core User’s Manual, version 6.0, Sony Computer Entertainment Inc., pp. 29, 65, 67, 122, 124-125, 139-140.