Examples for Verik. Refer to template for a template project. Compiling the examples requires a local build of the Verik toolchain.
RISC-V core adapted from the PicoRV32 project.
PicoRV32 is a CPU core that implements the RV32IMC instruction set.
It is configurable with an optional interrupt controller, single or two-cycle ALU, and single or dual-port register
file.
Tags: #Modules #Parameterization #Assertions
Examples that are meant to be run on the Nexys 4, a development board with an Artix-7 FPGA. These examples are synthesized with Xilinx Vivado and may integrate Vivado IP.
Simple seven-segment display driver with test bench.
Tags: #FPGA #Modules
Write data from a camera into block memory and read from the memory to drive a VGA display.
Tags: #FPGA #Modules
Read audio input from an ADC, perform an FFT, and plot the magnitudes on a VGA display.
Tags: #FPGA #Modules
Examples adapted from The UVM Primer that demonstrate OOP testbench
functionality.
These examples import from the UVM and closely follow the original SystemVerilog
coding conventions rather than the coding conventions of idiomatic Verik.
Warnings from code style violations are
suppressed with
@file:Suppress annotations at the top of the source files.
To compile these examples define the environment variable UVM_HOME and point it to uvm/distrib.
Conventional testbench for an ALU.
Tags: #Modules #Coverage
Interfaces and bus functional models for an ALU.
Tags: #Modules #ModuleInterfaces #Coverage
Classes and inheritance for a rectangle class.
Tags: #Classes
Polymorphic types for an animal class.
Tags: #Classes
Static methods with objects.
Tags: #Classes
Type parameterized classes.
Tags: #Classes #Parameterization
Factory pattern for object instantiation.
Tags: #Classes #Parameterization
Basic OOP testbench for an ALU.
Tags: #Modules #ModuleInterfaces #Classes #Coverage
Basic UVM testbench for an ALU.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage
UVM testbench for an ALU with UVM components.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage
UVM testbench for an ALU with UVM environments.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage
Dice roller example with UVM analysis ports.
Tags: #Importer #UVM #Coverage #Randomization
UVM testbench for an ALU with UVM analysis ports.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage
Interthread communication with UVM put and get ports.
Tags: #Importer #UVM
UVM testbench for an ALU with UVM put and get ports.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage
UVM testbench for an ALU with UVM reporting macros.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage
Deep operations for copying and converting objects to strings.
Tags: #Classes
UVM testbench for an ALU with UVM transactions.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage #Randomization
UVM testbench for an ALU with UVM agents.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage #Randomization
UVM testbench for an ALU with UVM sequences.
Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage #Randomization
Examples from uvmprimer rewritten to follow the coding conventions of idiomatic Verik.
These examples do not import from the UVM and implement the equivalent functionality directly in Verik.
Conventional testbench for an ALU.
Tags: #Modules #Coverage
Interfaces and bus functional models for an ALU.
Tags: #Modules #ModuleInterfaces #Coverage
Classes and inheritance for a rectangle class.
Tags: #Classes
Polymorphic types for an animal class.
Tags: #Classes
Static methods with objects.
Tags: #Classes
Type parameterized classes.
Tags: #Classes #Parameterization
Factory pattern for object instantiation.
Tags: #Classes #Parameterization
Basic OOP testbench for an ALU.
Tags: #Modules #ModuleInterfaces #Classes #Coverage
Deep operations for copying and converting objects to strings.
Tags: #Classes
Examples adapted from SystemVerilog for Verification that demonstrate more verification features. These examples follow the coding conventions of idiomatic Verik.
Arbiter testbench with a module interface that demonstrates module ports and clocking blocks.
Tags: #Modules #ModuleInterfaces
Generate an random array with unique elements.
Tags: #Classes #Randomization
ATM switch with test bench. The number of RX and TX streams is parameterized.
Tags: #Modules #ModuleInterfaces #Classes #Parameterization #Randomization
UTOPIA bus ATM switch with testbench. This example is currently work in progress.
Tags: #Modules #ModuleInterfaces #Classes #Parameterization #Coverage #Randomization
Miscellaneous examples that demonstrate various aspects of the language.
Simple counter module.
Tags: #Module
Simple parameterized ripple-carry adder module.
Tags: #Module #Parameterization
Simple combinational and sequential multipliers.
Tags: #Module
Various combinational logic expressed with simple logic gates.
Tags: #Module
Simple RV32I ALU with tests.
Tags: #Module
Direct mapped write-back cache.
Tags: #Module #ModuleInterface