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trans-mem.c (gate_tm_init): Return false if cfun->cfg is NULL. #29

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trans-mem.c (gate_tm_init): Return false if cfun->cfg is NULL. #29

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taskset
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@taskset taskset commented Sep 6, 2018

make gate_tm_init more robust and avoid this bug:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87162

@jwakely
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jwakely commented Oct 2, 2018

This is an unofficial mirror that nobody from the GCC project is involved with. Sending pull requests here is a waste of time.

Please see https://gcc.gnu.org/contribute.html for how to contribute to GCC, thanks.

@skeetor
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skeetor commented Feb 17, 2019

So whats the point of this mirror?

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jwakely commented Mar 8, 2019

I don't know. Somebody thought it would be useful to have a copy of GCC mirrored on github.

nstester pushed a commit to nstester/gcc that referenced this pull request May 18, 2023
@Stammark
arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
8eedd1e 
Hi all,

We noticed that calls to the vadcq and vsbcq intrinsics, both of
which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
the FPSCR, would produce the following code:

```
< r2 is the *carry input >
vmrs	r3, FPSCR_nzcvqc
bic	r3, r3, #536870912
orr	r3, r3, r2, lsl gcc-mirror#29
vmsr	FPSCR_nzcvqc, r3
```

when the MVE ACLE instead gives a different instruction sequence of:
```
< Rt is the *carry input >
VMRS Rs,FPSCR_nzcvqc
BFI Rs,Rt,gcc-mirror#29,#1
VMSR FPSCR_nzcvqc,Rs
```

the bic + orr pair is slower and it's also wrong, because, if the
*carry input is greater than 1, then we risk overwriting the top two
bits of the FPSCR register (the N and Z flags).

This turned out to be a problem in the header file and the solution was
to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
that we only care about the lowest bit and can optimise to a BFI.

Ok for trunk?

Thanks,
Stam Markianos-Wright

gcc/ChangeLog:

	* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
	(__arm_vadcq_u32): Likewise.
	(__arm_vadcq_m_s32): Likewise.
	(__arm_vadcq_m_u32): Likewise.
	(__arm_vsbcq_s32): Likewise.
	(__arm_vsbcq_u32): Likewise.
	(__arm_vsbcq_m_s32): Likewise.
	(__arm_vsbcq_m_u32): Likewise.
	* config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.

gcc/testsuite/ChangeLog:
	* gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New.
kraj pushed a commit to kraj/gcc that referenced this pull request May 18, 2023
@Stammark
arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
f51bc07 
Hi all,

We noticed that calls to the vadcq and vsbcq intrinsics, both of
which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
the FPSCR, would produce the following code:

```
< r2 is the *carry input >
vmrs	r3, FPSCR_nzcvqc
bic	r3, r3, #536870912
orr	r3, r3, r2, lsl gcc-mirror#29
vmsr	FPSCR_nzcvqc, r3
```

when the MVE ACLE instead gives a different instruction sequence of:
```
< Rt is the *carry input >
VMRS Rs,FPSCR_nzcvqc
BFI Rs,Rt,gcc-mirror#29,#1
VMSR FPSCR_nzcvqc,Rs
```

the bic + orr pair is slower and it's also wrong, because, if the
*carry input is greater than 1, then we risk overwriting the top two
bits of the FPSCR register (the N and Z flags).

This turned out to be a problem in the header file and the solution was
to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
that we only care about the lowest bit and can optimise to a BFI.

Ok for trunk?

Thanks,
Stam Markianos-Wright

gcc/ChangeLog:

	* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
	(__arm_vadcq_u32): Likewise.
	(__arm_vadcq_m_s32): Likewise.
	(__arm_vadcq_m_u32): Likewise.
	(__arm_vsbcq_s32): Likewise.
	(__arm_vsbcq_u32): Likewise.
	(__arm_vsbcq_m_s32): Likewise.
	(__arm_vsbcq_m_u32): Likewise.
	* config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.

gcc/testsuite/ChangeLog:
	* gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New.

(cherry picked from commit f1417d051be094ffbce228e11951f3e12e8fca1c)
kraj pushed a commit to kraj/gcc that referenced this pull request May 18, 2023
@Stammark
arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags
1ad81fc 
Hi all,

We noticed that calls to the vadcq and vsbcq intrinsics, both of
which use __builtin_arm_set_fpscr_nzcvqc to set the Carry flag in
the FPSCR, would produce the following code:

```
< r2 is the *carry input >
vmrs	r3, FPSCR_nzcvqc
bic	r3, r3, #536870912
orr	r3, r3, r2, lsl gcc-mirror#29
vmsr	FPSCR_nzcvqc, r3
```

when the MVE ACLE instead gives a different instruction sequence of:
```
< Rt is the *carry input >
VMRS Rs,FPSCR_nzcvqc
BFI Rs,Rt,gcc-mirror#29,#1
VMSR FPSCR_nzcvqc,Rs
```

the bic + orr pair is slower and it's also wrong, because, if the
*carry input is greater than 1, then we risk overwriting the top two
bits of the FPSCR register (the N and Z flags).

This turned out to be a problem in the header file and the solution was
to simply add a `& 1x0u` to the `*carry` input: then the compiler knows
that we only care about the lowest bit and can optimise to a BFI.

Ok for trunk?

Thanks,
Stam Markianos-Wright

gcc/ChangeLog:

	* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
	(__arm_vadcq_u32): Likewise.
	(__arm_vadcq_m_s32): Likewise.
	(__arm_vadcq_m_u32): Likewise.
	(__arm_vsbcq_s32): Likewise.
	(__arm_vsbcq_u32): Likewise.
	(__arm_vsbcq_m_s32): Likewise.
	(__arm_vsbcq_m_u32): Likewise.
	* config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.

gcc/testsuite/ChangeLog:
	* gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New.
tschwinge added a commit to tschwinge/gcc that referenced this pull request Sep 4, 2023
@tob2 @tschwinge
Add 'libgomp.c-c++-common/pr100059-1.c'
fe0f9e0 
For nvptx offloading, it'll FAIL its execution test until nvptx-tools updated
to include commit 1b5946d78ef5dcfb640e9f545a7c791b7f623911
"Merge commit '26095fd01232061de9f79decb3e8222ef7b46191' into HEAD [gcc-mirror#29]",
<SourceryTools/nvptx-tools@1b5946d>.

	libgomp/
	* testsuite/libgomp.c-c++-common/pr100059-1.c: New.

Co-authored-by: Thomas Schwinge <thomas@codesourcery.com>
cooljeanius referenced this pull request in cooljeanius/gcc Sep 20, 2024
@cooljeanius @github-advanced-security
Fix code scanning alert #29: Incorrect conversion between integer types
0f5ca01 
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
cooljeanius referenced this pull request in cooljeanius/gcc Sep 20, 2024
@cooljeanius
Merge pull request #22 from cooljeanius/autofix/alert-29-1820ad9861
8e4c3c3 
Fix code scanning alert #29: Incorrect conversion between integer types
cooljeanius referenced this pull request in cooljeanius/gcc Sep 20, 2024
@cooljeanius @github-advanced-security
Fix code scanning alert #29: Incorrect conversion between integer types
e54dda1 
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
cooljeanius referenced this pull request in cooljeanius/gcc Sep 20, 2024
@cooljeanius
Merge pull request #23 from cooljeanius/autofix/alert-29-4a1d6f38fd
352d03e 
Fix code scanning alert #29: Incorrect conversion between integer types
iains pushed a commit to NinaRanns/gcc that referenced this pull request Oct 28, 2024
@villevoutilainen
Merge pull request gcc-mirror#29 from iains/contracts-nonattr-p1494r4
b6ed54a 
Contracts nonattr p1494r4
hubot pushed a commit that referenced this pull request Nov 8, 2024
@Torbjorn-Svensson
testsuite: arm: Use check-function-bodies in epilog-1.c test
ec86e87 
Update test case for armv8.1-m.main that supports conditional
arithmetic.

armv7-m:
        push    {r4, lr}
        ldr     r4, .L6
        ldr     r4, [r4]
        lsls    r4, r4, #29
        it      mi
        addmi   r2, r2, #1
        bl      bar
        movs    r0, #0
        pop     {r4, pc}

armv8.1-m.main:
        push    {r3, r4, r5, lr}
        ldr     r4, .L5
        ldr     r5, [r4]
        tst     r5, #4
        csinc   r2, r2, r2, eq
        bl      bar
        movs    r0, #0
        pop     {r3, r4, r5, pc}

gcc/testsuite/ChangeLog:

	* gcc.target/arm/epilog-1.c: Use check-function-bodies.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
hubot pushed a commit that referenced this pull request Nov 8, 2024
@Torbjorn-Svensson
testsuite: arm: Use check-function-bodies in epilog-1.c test
7244465 
Update test case for armv8.1-m.main that supports conditional
arithmetic.

armv7-m:
        push    {r4, lr}
        ldr     r4, .L6
        ldr     r4, [r4]
        lsls    r4, r4, #29
        it      mi
        addmi   r2, r2, #1
        bl      bar
        movs    r0, #0
        pop     {r4, pc}

armv8.1-m.main:
        push    {r3, r4, r5, lr}
        ldr     r4, .L5
        ldr     r5, [r4]
        tst     r5, #4
        csinc   r2, r2, r2, eq
        bl      bar
        movs    r0, #0
        pop     {r3, r4, r5, pc}

gcc/testsuite/ChangeLog:

	* gcc.target/arm/epilog-1.c: Use check-function-bodies.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit ec86e87)
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3 participants
@taskset @jwakely @skeetor