libstdc++: Use aligned_alloc instead of memalign for newlib #86
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The existing TypeInfo errors can be cryptic. This alters the diagnostic to include which expression is requiring `object.TypeInfo'. gcc/d/ChangeLog: * d-tree.h (check_typeinfo_type): Add Expression* parameter. (build_typeinfo): Likewise. Declare new override. * expr.cc (ExprVisitor): Call build_typeinfo with Expression*. * typeinfo.cc (check_typeinfo_type): Include expression in the diagnostic message. (build_typeinfo): New override. gcc/testsuite/ChangeLog: * gdc.dg/rtti1.d: New test. (cherry picked from commit e55eda2)
The SINGLE_BIT_MASK_OPERAND() is overly restrictive, triggering for bits above 31 only (to side-step any issues with the negative SImode value 0x80000000/(-1ull << 31)/(1 << 31)). This moves the special handling of this SImode value (i.e. the check for (-1ull << 31) to riscv.cc and relaxes the SINGLE_BIT_MASK_OPERAND() test. With this, the code-generation for loading (1ULL << 31) from: li a0,1 slli a0,a0,31 to: bseti a0,zero,31 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as (-1 << 31) for the single-bit case, when operating on (1 << 31) in SImode. * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for any single-bit value, moving the special case for (1 << 31) to riscv_build_integer_1 (in riscv.c). Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> (cherry picked from commit 4e72cca)
Since F16C and VAES are only usable with AVX, require AVX for F16C and VAES. libgcc/105920 * common/config/i386/cpuinfo.h (get_available_features): Require AVX for F16C and VAES. (cherry picked from commit 751f306)
The macOS 13 SDK (and equivalent-version iOS and other Apple OS SDKs)
contain this definition in <sys/cdefs.h>:
863 #define __null_terminated
This collides with the use of __null_terminated in libstdc++'s
experimental fs_path.h.
As libstdc++'s use of this token is entirely internal to fs_path.h, the
simplest workaround, renaming it, is most appropriate. Here, it's
renamed to __nul_terminated, referencing the NUL ('\0') value that is
used to terminate the strings in the context in which this tag structure
is used.
libstdc++-v3/ChangeLog:
* include/experimental/bits/fs_path.h (__detail::__null_terminated):
Rename to __nul_terminated to avoid colliding with a macro in
Apple's SDK.
Signed-off-by: Mark Mentovai <mark@mentovai.com>
(cherry picked from commit 254e88b)
This is LWG 3220 which is about to become Tentatively Ready. libstdc++-v3/ChangeLog: * include/std/atomic (__atomic_val_t): Use __type_identity_t instead of atomic<T>::value_type, as per LWG 3220. * testsuite/29_atomics/atomic/lwg3220.cc: New test. (cherry picked from commit 30cc1b6)
(In reply to Uroš Bizjak from comment #1) > Instruction does not accept memory operand for operand 3: > > (define_insn_and_split > "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint" > [(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x") > (unspec:<ssebytemode> > [(match_operand:<ssebytemode> 1 "register_operand" "0,0,x") > (match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm") > (subreg:<ssebytemode> > (lt:VI48_AVX > (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x") > (match_operand:VI48_AVX 4 "const0_operand")) 0)] > UNSPEC_BLENDV))] > > The problematic insn is: > > (define_insn_and_split "*avx_cmp<mode>3_ltint_not" > [(set (match_operand:VI48_AVX 0 "register_operand") > (vec_merge:VI48_AVX > (match_operand:VI48_AVX 1 "vector_operand") > (match_operand:VI48_AVX 2 "vector_operand") > (unspec:<avx512fmaskmode> > [(subreg:VI48_AVX > (not:<ssebytemode> > (match_operand:<ssebytemode> 3 "vector_operand")) 0) > (match_operand:VI48_AVX 4 "const0_operand") > (match_operand:SI 5 "const_0_to_7_operand")] > UNSPEC_PCMP)))] > > which gets split to the above pattern. > > In the preparation statements we have: > > if (!MEM_P (operands[3])) > operands[3] = force_reg (<ssebytemode>mode, operands[3]); > operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode); > > Which won't fly when operand 3 is memory operand... > gcc/ChangeLog: PR target/105953 * config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg operands[3]. gcc/testsuite/ChangeLog: * g++.target/i386/pr105953.C: New test.
Prevents them from triggering warnings when compiling with `-Wpadded'. gcc/d/ChangeLog: * typeinfo.cc (make_internal_typeinfo): Set TYPE_ARTIFICIAL. gcc/testsuite/ChangeLog: * gdc.dg/Wpadded.d: New test. (cherry picked from commit 57b2ada)
An empty g++ command line should produce a diagnostic that there are no inputs. The PR is that currently Darwin produces a dignostic about missing link items instead - this is because (errnoeously), for this driver, we are creating a link job for empty command lines. The problem occurs in four stages: The g++ driver appends -shared-libgcc to the command line. The Darwin driver_init code in the backend does not see this (it sees an empty command line). When the back end driver code driver sees an empty command line, it does not add any supplementary flags (e.g. asm-macosx-version-min) - precisely to avoid anything being claimed as an input_file and therefore triggering a link line. Since we do not have a value for asm-macosx-version-min when processing the driver specs, we unconditionally inject 'multiply_defined suppress' which is used with shared libgcc (but only intended on very old Darwin). This then causes the generation of a link job. The solution, for the present, is to move version-specific link params to the LINK_SPEC so that they are only processed when a link job has already been decided. Signed-off-by: Iain Sandoe <iain@sandoe.co.uk> PR target/105599 gcc/ChangeLog: * config/darwin.h: Move versions-specific handling of multiply_defined from SUBTARGET_DRIVER_SELF_SPECS to LINK_SPEC. (cherry picked from commit 7947379)
f18cbc1 (2021-12-18) updated various parts of gcc to not impose a Darwin or macOS version maximum of the current known release. Different parts of gcc accept, variously, Darwin version numbers matching darwin2*, and macOS major version numbers up to 99. The current released version is Darwin 21 and macOS 12, with Darwin 22 and macOS 13 expected for public release later this year. With one major OS release per year, this strategy is expected to provide another 8 years of headroom. However, f18cbc1 missed config/darwin-c.c (now .cc), which continued to impose a maximum of macOS 12 on the -mmacosx-version-min compiler driver argument. This was last updated from 11 to 12 in 11b9675 (2021-10-27), but kicking the can down the road one year at a time is not a viable strategy, and is not in line with the more recent technique from f18cbc1. Prior to 556ab51 (2020-11-06), config/darwin-c.c did not impose a maximum that needed annual maintenance, as at that point, all macOS releases had used a major version of 10. The stricter approach imposed since then was valuable for a time until the particulars of the new versioning scheme were established and understood, but now that they are, it's prudent to restore a more permissive approach. gcc/ChangeLog: * config/darwin-c.cc: Make -mmacosx-version-min more future-proof. Signed-off-by: Mark Mentovai <mark@mentovai.com> (cherry picked from commit 6725f18)
In common with system tools, GCC uses a version obtained from the kernel as the prevailing macOS target, when that is not overridden by command line or environment versions (i.e. mmacosx-version-min=, MACOSX_DEPLOYMENT_TARGET). Presently, GCC assumes that if the OS version is >= 20, the value used should include both major and minium version identifiers. However the system tools (for those versions) truncate the value to the major version - this leads to link errors when combining objects built with clang and GCC for example: ld: warning: object file (null.o) was built for newer macOS version (12.2) than being linked (12.0) The change here truncates the values GCC uses to the major version. gcc/ChangeLog: PR target/104871 * config/darwin-driver.cc (darwin_find_version_from_kernel): If the OS version is darwin20 (macOS 11) or greater, truncate the version to the major number. (cherry picked from commit add1ada)
The code in gen_cpymem_ldrd_strd has been incorrect for big-endian since r230663. The problem is that we use gen_lowpart, etc. to split the 64-bit quantity, but fail to account for the fact that these routines are really dealing with 64-bit /values/ and in big-endian the ordering of the sub-registers changes. To fix this, I've renamed the conceptually misnamed low_reg and hi_reg as first_reg and second_reg, and then used different logic for big-endian targets to initialize these values. This makes the logic clearer than trying to think about high bits and low bits. gcc/ChangeLog: PR target/105981 * config/arm/arm.cc (gen_cpymem_ldrd_strd): Rename low_reg and hi_reg to first_reg and second_reg respectively. Initialize them correctly when generating big-endian code. (cherry picked from commit 8aaa948)
…5871] As the following testcase shows, BIT_FIELD_REF result doesn't have to have just integral type, it can also have vector type. And in that case cxx_eval_bit_field_ref just ICEs on it because it is unprepared for that case, creates the initial value with build_int_cst (sure, that one could be easily replaced with build_zero_cst) and then expects it can through shifts, ands and ors come up with the final value, but that doesn't work for vectors. We already call fold_ternary if whole is a VECTOR_CST, this patch does the same if the result doesn't have integral type. And, there is no guarantee fold_ternary will succeed and the callers certainly don't expect NULL being returned, so it also diagnoses those as non-constant and returns original t in that case. 2022-06-09 Jakub Jelinek <jakub@redhat.com> PR c++/105871 * constexpr.cc (cxx_eval_bit_field_ref): For BIT_FIELD_REF with non-integral result type use fold_ternary too like for BIT_FIELD_REFs from VECTOR_CST. If fold_ternary returns NULL, diagnose non-constant expression, set *non_constant_p and return t, instead of returning NULL. * g++.dg/pr105871.C: New test. (cherry picked from commit 4c334e0)
Check for volatile flag to ipa_load_from_parm_agg. gcc/ChangeLog: 2022-06-10 Jan Hubicka <hubicka@ucw.cz> PR ipa/105739 * ipa-prop.cc (ipa_load_from_parm_agg): Punt on volatile loads. gcc/testsuite/ChangeLog: 2022-06-10 Jan Hubicka <hubicka@ucw.cz> * gcc.dg/ipa/pr105739.c: New test. (cherry picked from commit 8f6c317)
Both IFN_ATOMIC_BIT_TEST_AND_* and IFN_ATOMIC_*_FETCH_CMP_0 ifns are matched if their corresponding optab is implemented for the particular mode. The fact that those optabs are implemented doesn't guarantee they will succeed though, they can just FAIL in their expansion. The expansion in that case uses expand_atomic_fetch_op as fallback, but as has been reported and and can be reproduced on the testcases, even those can fail and we didn't have any fallback after that. For IFN_ATOMIC_BIT_TEST_AND_* we actually have such calls. One is done whenever we lost lhs of the ifn at some point in between matching it in tree-ssa-ccp.cc and expansion. The following patch for that case just falls through and expands as if there was a lhs, creates a temporary for it. For the other expand_atomic_fetch_op call in the same expander and for the only expand_atomic_fetch_op call in the other, this falls back the hard way, by constructing a CALL_EXPR to the call from which the ifn has been matched and expanding that. Either it is lucky and manages to expand inline, or it emits a libatomic API call. So that we don't have to rediscover which builtin function to call in the fallback, we record at tree-ssa-ccp.cc time gimple_call_fn (call) in an extra argument to the ifn. 2022-06-16 Jakub Jelinek <jakub@redhat.com> PR middle-end/105951 * tree-ssa-ccp.cc (optimize_atomic_bit_test_and, optimize_atomic_op_fetch_cmp_0): Remember gimple_call_fn (call) as last argument to the internal functions. * builtins.cc (expand_ifn_atomic_bit_test_and): Adjust for the extra call argument to ifns. If expand_atomic_fetch_op fails for the lhs == NULL_TREE case, fall through into the optab code with gen_reg_rtx (mode) as target. If second expand_atomic_fetch_op fails, construct a CALL_EXPR and expand that. (expand_ifn_atomic_op_fetch_cmp_0): Adjust for the extra call argument to ifns. If expand_atomic_fetch_op fails, construct a CALL_EXPR and expand that. * gcc.target/i386/pr105951-1.c: New test. * gcc.target/i386/pr105951-2.c: New test. (cherry picked from commit 6a27c43)
…__builtin_shufflevector handling [PR106001] In this case the STATIC_CAST_EXPR expressions in the call aren't type nor value dependent, but maybe_constant_value still ICEs on those when processing_template_decl. Calling fold_non_dependent_expr on it instead fixes the ICE and folds them to INTEGER_CSTs. 2022-06-17 Jakub Jelinek <jakub@redhat.com> PR c++/106001 * typeck.cc (build_x_shufflevector): Use fold_non_dependent_expr instead of maybe_constant_value. * g++.dg/ext/builtin-shufflevector-4.C: New test. (cherry picked from commit a284fad)
The following testcase ICEs because there is NON_LVALUE_EXPR (location
wrapper) around a VAR_DECL and has TYPE_MODE V2SImode and
SCALAR_INT_TYPE_MODE on that ICEs. Or for -m32 -march=i386 TYPE_MODE
is DImode, but SCALAR_INT_TYPE_MODE still uses the raw V2SImode and ICEs
too.
2022-06-18 Jakub Jelinek <jakub@redhat.com>
PR middle-end/105998
* varasm.cc (narrowing_initializer_constant_valid_p): Check
SCALAR_INT_MODE_P instead of INTEGRAL_MODE_P, also break on
! INTEGRAL_TYPE_P and do the same check also on op{0,1}'s type.
* c-c++-common/pr105998.c: New test.
(cherry picked from commit ef66212)
The mode of pointer argument should equal ptr_mode, not Pmode. 2022-06-17 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/105970 * config/i386/i386.cc (ix86_function_arg): Assert that the mode of pointer argumet is equal to ptr_mode, not Pmode. gcc/testsuite/ChangeLog: PR target/105970 * gcc.target/i386/pr105970.c: New test. (cherry picked from commit 1f8278b)
This patch introduces alpha-specific version of store_data_bypass_p that ignores TRAP_IF that would result in assertion failure (and internal compiler error) in the generic store_data_bypass_p function. While at it, also remove ev4_ist_c reservation, store_data_bypass_p can handle the patterns with multiple sets since some time ago. 2022-06-17 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/105209 * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New. * config/alpha/alpha.cc (alpha_store_data_bypass_p): New function. (alpha_store_data_bypass_p_1): Ditto. * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead of generic store_data_bypass_p. (ev4_ist_c): Remove insn reservation. gcc/testsuite/ChangeLog: PR target/105209 * gcc.target/alpha/pr105209.c: New test. (cherry picked from commit cc378e6)
Disallow siball when calling ifunc functions with PIC register so that PIC register can be restored. gcc/ PR target/105960 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Return false if PIC register is used when calling ifunc functions. gcc/testsuite/ PR target/105960 * gcc.target/i386/pr105960.c: New test. (cherry picked from commit fe9765c)
As PR105940 shown, when rs6000 port tries to assign
m_suggested_unroll_factor by 4 or so, there will be ICE on:
exact_div (LOOP_VINFO_VECT_FACTOR (loop_vinfo),
loop_vinfo->suggested_unroll_factor);
In function vect_analyze_loop_2, the current place of
suggested_unroll_factor applying can't guarantee it's
applied for all cases. As the case shows, vectorizer
could retry with SLP forced off, the vf is reset by
saved_vectorization_factor which isn't applied with
suggested_unroll_factor before. It means it can end
up with one vf which neglects suggested_unroll_factor.
I think it's off design, we should move the applying
of suggested_unroll_factor after start_over.
PR tree-optimization/105940
gcc/ChangeLog:
* tree-vect-loop.cc (vect_analyze_loop_2): Move the place of
applying suggested_unroll_factor after start_over.
(cherry picked from commit f907cf4)
Apply the patches that are provided in the crosstool-ng GCC 12.2.0 package. 0000-libtool-leave-framework-alone.patch 0001-gcc-plugin-POSIX-include-sys-select-h.patch 0002-arm-softfloat-libgcc.patch 0003-libgcc-disable-split-stack-nothreads.patch 0004-Remove-use-of-include_next-from-c-headers.patch Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This adds the necessary bits to build for x86_64-zephyr-elf with multilib support (m32 and m64), following the x86_64-*-linux* footsteps. Signed-off-by: Kumar Gala <kumar.gala@linaro.org> Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This is a porting of the patches in meta-zephyr-sdk to gcc-8.2.0 We merge: recipes-devtools/gcc/files/libgcc-t-zephyr.patch recipes-devtools/gcc/files/config-x86-multi-gcc.patch recipes-devtools/gcc/files/x86-multilib.patch recipes-devtools/gcc/files/config-libgcc-softfp.patch Into one patch. There are some changes to libgcc/config.host in gcc-8.2.0 that required updating the patch to that file. There's some common code to handle soft-fp on x86. In gcc-8.2.0 that common code would by default get applied to a zephyr build. However the common code doesn't handle soft-fp the way we need so we add i[34567]86-zephyr-elf as a special case similar to i[34567]86-*-elfiamcu. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds the necessary bits for building libraries for the LEON -mcpu targets. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This fixes soft-float build for x86 32-bit (-m32 -msoft-float) under x86_64-zephyr-elf multilib build. This now actually includes the soft float functions. Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds a Zephyr-specific multilib configuration file for the RISC-V architecture in order to ensure that the multilibs are built for all RISC-V targets supported in the upstream Zephyr RTOS. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the following base instruction set multilibs that can be used for every practical extension permutation: * rv32i_zicsr_zifencei * rv32e_zicsr_zifencei * rv64i_zicsr_zifencei These base instruction set multilibs are mapped to the compatible extension permutations that do not have a dedicated multilib in order to increase the ISA coverage of the toolchain. Note that the Zicsr and Zifencei extensions are still specified for the base instruction set multilibs because the Zephyr RISC-V architecture port requires them and it is not practical to configure a RISC-V core that does not support these instruction sets. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the following multilibs that support the target configurations with the bit manipulation (Bitmanip) extension: * rv32im_zicsr_zifencei_zba_zbb_zbc_zbs * rv32emc_zicsr_zifencei_zba_zbb_zbc_zbs * rv64im_zicsr_zifencei_zba_zbb_zbc_zbs * rv64imac_zicsr_zifencei_zba_zbb_zbc_zbs These multilibs are mapped to the other compatible target configurations to improve the configuration coverage. This commit also adds a new non-Bitmanip capable multilib for the `rv64im_zicsr_zifencei` in order to better align the coverage of the RV64I to that of the RV32I. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit includes the ARC patches from the zephyr-gcc12 branch of the foss-for-synopsys-dwc-arc-processors/gcc repository, the commits from 95370809fff1cf77839f5f6440d0602bcdc4b542 to e65f77588ccb6b5b3f9f84345772ec419d99d169: [ARCx] Configurations [ARCx] Populate constraints and predicates. [ARCx] Add subroutine calls [ARCx] Add placeholder in the md file Added constraints for short immediate variations. [ARCx] Update calls and sibcalls Changed name of constraints. update compare Push for compilation Added macros for constraints verification. Fixes Got the cc1! Cleanup #1 [ARCx] Add frame info and prologue expand [ARCx] Add FUNCTION_VALUE hook First commit with arith define_insns. Forgot to change type list. [ARCx] Fix addsi3 in arith.md Add expand epilogue functions [ARCx] arc64_mov insns have been added [ARCx] Keep the fixes on generated MD's separated [ARCx] Usefull hacks [ARCx] Make it compliable again Added logic instruction rules (most of them). Removed include arith.md from arc64.md. Left logic.md. [ARCx] Introduce push/pop to arc64.md and more [ARCx] Add a hand-crafted arith.md [ARCx] Add target hooks for printing operands [ARCx] Use ldb/ldh and stb/sdh for movqi/hi [ARCx] Add the missing arith.md (hand-crafted one) [ARCx] Add movdi (the 64 bit move) [ARCx] More on calling convention [ARCx] Fix SP popping issue and use movl for movdi [ARCx] Treat SP register as a general register [ARCx] Add airthmatic instructins for DImode [ARCx] Reove unused passes [ARCx] Update print_operand and print_operand_address [ARCx] LIBGCC attempt adding configuration [ARCx] Fix emitting labels and aligns [ARCx] movqi: Add w6 immediate store [ARCx] Add the first ARC64 test (movqi) [ARCx] Update compare, signext and hooks (newlib) [ARCx] Fix type in .md for signext [ARCx] Extend test01 of movq [ARCx] add more test cases for movq Fixes [ARCx] break movq test [ARCx] enable movq-6 fix 2 [ARCx] mark movq-2 as fixed [ARCx] Add support to movq: immediate to memory Update sign/zero extend patterns, fail for FP ops [ARCx] Fix typo in movq-9 [MOV] Update movqi and movhi patterns. [LENGTH] Compute the length for st/ld type of instructions. [ARCx] update in movq tests. [LENGTH] Remove dead code and negate bool correctly. [ARCx] Add and, xor, ior, smin, smax, not, abs expands (and insns) [FIX] small fix in the template for LOGIC2 ops [FIX] Floats are passed in mem, fix rotatert. [ARCx] Improve on movq. [TST] Fix movq-2.c [FLOAT] Add a soft float move sf. [MD] Add movhi along with tests. [TST] Fix movh-6 test [TST] Add FIXMEs to the tests Comment out unimplemented expands [DBG] Emmit a mov sp,fp regardless of the offset [MD] Add movdi along with the tests Added libnosys to GCC specs. Fixed constraints to arc64_movqi. Fixed most of the issues with undefined references. [SYMBOLS] Split a 64bit symbol/const_int into hi/lo_sum. Don't return more than one reg Commented rule to fix zero_extend issues in dejagnu. Only return simple scalar datatypes Add trampolines Add iscompact attribute to jump Added all the soft insns to libgcc needed for DejaGNU tests. Fix computing frame size Fix restoring regs Fix restore regs Changed back to 8 the units per word for libgcc. Add muldi3 function Add div/mod 64bit routines Handle 64bit constants on ARITH ops Add arc64_nonmem_operand predicate More on handling 64bit constants Change stack boundary to 64 [MD] Swap dst and src for sign extend Add Sibcall hook fix splitting 64 bit constants Handle 64bit constants for CMP instructions Add 32bit variant for clz, ctz, ffs, parity and popcount Handle SP updates with large 64bit constants. Fix anon args Fix tests Improve trampoline [CTOR/DTOR] link with crti,crtend,crtbegin, and crtn [STACK] Align everything Update alignments, trampoline, and add dump stack info Fix trampoline. Cleanup attr-alloc_size-11.c XPASS Add partial bytes hook Fix typo [PIC] Add pic support for variables [PIC] Emit @plt for calls [PIC] Add small/large PIC memory model. [PIC] Disable -fPIC impl as it is not yet supported by tools. [TLS] Add basic TLS support. [ARC] LIBGCC: Allow configure for olde good 32-bit ARC (gcc-mirror#83) [SPEC] Add LINK_SPEC to elf Fixed issue related to offset size of conditional branch instructions. First builtins added to arc64 (nop, lr, sr, flag, brk). TI mode ADD and SUB pattern using respective carry instructions. arc64: Fix choosing short insn arc64: Add shifted adds and subs ops arc64: fix bcc_s instructions arc64: Add DIV/REM 32/64 instructions arc64: add mpy(l) instructions arc: add dbnz pattern arc64: add short version instruction. add new insns typo fix arc64: fix printing Low nibble needs to be unsigned. arc64: Add rotate variants arc64: Generate reg index and scalled accesses arc64: experimental 2 regs/address arc64:non functional insn_cost arc64: CMP0: and,ior,xor, sex, ext arc64: add scalled s9 support arc64: scalled shimm for add/minus arc64: Add conditional execution arc64: CSTORE force to register large constants. arc64: Add short mov,ld, and st instructions arc64: Remove F16_OP_IMM instructions arc64: fix builtins pattern, types and expand routines arc64: Add C/C++ preprocessor defines arc64: Fix cmpsi' s3 short insn constraint. arc64: Honor memory model large for calls. arc64: set sibcall returns size to 4 arc64: Remove unecesary attributes arc64: Emmit @u32 arc64: UNSPEC addresses are using limm arc64: Fix typo in call ce instructions arc64: Add basic DWARF macros arc64: Add exception handling support. arc64:fix setcc instructions when dealing with 64bit imm arc64:fix crtstuff to use proper 64bit pointers arc64: Add dummy mcpu option arc64: fix: Memory operands are using implicit brackets arc64: Add linux configuration arc64: Update to gcc 10 release arc64: Add MI_THUNK output. arc64: baremetal doesn't use dwarf unwinding arc64: Use pc-rel addressing also for non-pic medium symbols arc64: Rename ARC64_UNSPEC_GOTOFF to ARC64_UNSPEC_PCREL arc64: Update combiner patterns arc64: Add reload variant for dbnz instruction arc64: Add R30 as epilogue used when TLS arc64: Tell to the compiler we want DWARF2 arc64:Implement EH_USES when TP is used. arc64: fix tls detection in assembler ar64: hack: The file I/O doesn't fully work for nsim64 arc64: Add btst, sub.f and rsub.f. Improve ifcvt. Implementation of atomics for ARC64. arc64: Add doloop_end pattern. Implemented builtin for trap_s. arc64: Deal with out of bounds target for dbnz insn. Fix issue with atomics on glibc toolchain build. arc64: Accept SYM+OFFSET constants WIP for Review: Make atomic option enum arc64: Fix target tests. arc64: Atomic builtin only defined if we have atomic ops arc64: Check for atomic ops ARC64: atomics: enable baseline llock/scond (gcc-mirror#92) arc64: Code cleanup arc64: simple cleanup arc64: fix warning arc64: Accept only PCREL unspecs for mov instruction. arc64: Add table-jump support. arc64: Handle TLS unspecs more strictly arc64: Swap saving order for BLINK and FP arc64: Refurbish address gen for SMALL/MEDIUM mem types. arc64: fix 64bit address gen ARC64: builtin: generate a define for cmodel arc64: Cleanup atomic1 implementation arc64: Move static functions to beging of the file (txt cleanup) arc64: Add the new ARCv3 ATO instruction support. arc64: add unaligned access, improve addN patterns. arc64: Enable unaligned by default, add C-macro arc64: HACK: volatile pointers will use .di arc64: Remove mmpy64 option arc64: add missing hook. Improves code gen for 32 bit arc64: Remove compare with zero for mpyl insns arc64: Add bitscan instructions. arc64: Update predicate commutative ops, add zero-ext predicate ops. arc64: Use a larger value for MOVE_RATIO arc64: Add SRL/LRL builtins arc64: Address scaling cannot be used with pre/post address modifiers arc64: DIV/REM force to reg 64b immediates arc64: Enable div/rem instructions by default ARC64 Revert back to aligned data accesses only for now (gcc-mirror#94) arc64: Add SP floating point instructions. arc64: FP use stock legit addr. Introduce compiler macro. arc64: Re-enable jump table arc64: Add fnmadd fnmsub based patterns used when honoring zeros arc64: Add movcc and predicated fmov arc64: Disable movcc insns arc64: Another add<M> rA,rB,RC << M variant. Usefull for addr arc64: casesi: emit unlikely jump arc64: Add --with-fpu config option arc64: Turn on bitscan instructions. arc64: cleanup unused vars arc64: Add mov.f instruction arc64: Fix casesi snafu arc64: Refactor ABI, fix fpABI snafu arc64: Add IEEE half-precision support. arc64: don't use soft-fp routines for hf conversion arc64: Add support for half precision and integer vectors arc64: Add pack, mpy and vec extract instructions arc64: Fix FP vector patterns & add FMA ones arc64: Add vec_duplicate arc64: Fix warning arc64: Update softfp moves, fix warnings arc64: forgot this one revert atomic mod arc64: Add vector reduction pattern for 2xV arc64: Add Vectorizer cost hook. arc64: builtin-apply2 doesn't work with ARC64 FP ABI arc64: Add 64b SIMD fp support, and double precision fp hw support arc64: Fix matching scalled address. arc64: Add extra specs. arc64: Add msimd option which enables intSIMD instructions. arc64: disable incompatible test. arc64: f0-f7 are used to pass args in hard-floats ABI arc64: Add 128SIMD support. arc64: Add vect reduc pattern for v2si, use vadd2h/vsub2h for 16b ops. arc64: Add zero_extend patterns arc64: Provide a mapping from gcc regs to dwarf regs arc64: typo fix MAINLINE: Change test to check our vec_perm arc64: Add (integer) vector perm const arc64: Add int SIMD vec_shl, fix fp SIMD vec_extract arc64: Add m128 support for function's prologue/epilogue [multilib] Add a library for -m128 arc64: Initial cost control for loads/stores and most used patterns arc64: Fix immediate for mpy(u)w instructions. arc64: Fix mpy(u)w instruction arc64: Update split address for PRE_MOD addresses arc64: Using m128 in combination with mfpu defaults to mfpu libs arc64: Allow store instructions to store an imm. arc64: Update stl length to 8. arc64: Allow signed 32bit immediates for 64bit arith insns arc64: Use a long jump when crossing arc64: Add MAC/MACD/VMAC2H signed/unsigned instructions arc64: Increase div costs, encourage syntetic ones. arc64: type fix naming arc64: Update costs multiplication, addresses, and sgnext arc64: Add compare with 0 xbfu insns arc64: Fix xbfu.f operands arc64: Add patterns matching dmacwh[u], dmpywh[u] and dmach arc64: Improve matching .f instructions arc64: Add BBIT[0/1][L] pattern arc64: fix bbit range arc64: Add BRcc combiner patterns arc64: Use sign_extend when loading. arc64: fp: reused the ARCv2 C macros for code-diversity management (gcc-mirror#97) arc64: Add support for 34bit PLT calls m64/m128: Add cpymem expand arc64: Add delay slot scheduler arc64: Fix movmisalign patterns, and scale ld/st imms Remove unused files arc64: Remove 'Report'. arc64: Update madd instructions to avoid dead code removal. arc64: force to reg in vec_perm. arc64: Add dot to matomic option description. arc64: Update tests. arc64: memcpy: update move ratio values. arc64: Deal with 128b constants. arc64: Change maximum number of bytes to allow 128 moves. arc64: Remove duplicate macro arc64: Mark blink alive when emitting a call to __tls_get_addr arc64: Add PROFILE_HOOK arc64: add macro to signal Hard-float ABI (gcc-mirror#98) arc64: FP ABI update call used regs up to f15 arc64: Split 128b PIC addresses. arc64: Add convertions from HF to DF and back arc64: Fix mac constraints snafu. arc64: Use swap with v2hi vectors. arc64: Enable unaligned access for elf targets arc64: Add MPYD(U), change MULT costs. arc64: Fix dmpy int constraints arc64: Add dmpywh instruction (used scalar) arc64: Update accsi to accrn constraint arc64: Improve and fix potential issues with 16b scalar ops arc64: Update zero_ext cost, add new peephole pat arc64: Update zero extend from hi. arc64: Add sched info arc64: Fix addressing local symb (large) arc64: Use dedicated constraint for store type mems. arc64: Fix softfp move constraint letter snafu arc64: Fix snafu when computing ld/st insns sizes. arc64: Enable removable redundant extension instructions. arc64/arcv2: fix triplet snafu arc64: Add documentation. arc64: Update constraints arc64: Enforce the ld limm to be within 32bit range. arc64: Widen the scope for base/index regs arc64/arcv3: Check BE for TLS. arc64: Don't use implicit dmacwh(u) output. arc64: Add new mpyd/mac and mac/mac sched rules arc64: Disable speculation when filling delay slots arc64: TLS add a move before calling tls_get_addr arc64: Use a conservative size estimation for branches when computing loop body size. arc64: Introduce core register set arc64: Introduce a fallback path when dbnz target is too far [arc64] Add Exception handling builtins [arc64/libgcc] Unwinding out of signal handler arc64: Update dbnz's predicate and constraints arc64: Update store c-letters for vector ops arc64: Update FMA(s) instructions. Add Vector FP neg emulation arc64: Fix dmpywh<u> instructions with immediate operands. arc64: remove faulty add/sub 16b pattern arc64: Precompute TLS arc64: Consolidate pushl/popl instructions arc64: Add bswap32/64 ops arc64: Keep close MAC-MOV instructions arc64: Enable slow byte access for more efficient bitfield code. arc64: Use 'int' as base for wchar_t arc64: Add trap instruction arc64: Emit aq.rl flags for new AMOs. arc64: Use a PLUS operation while spliting the 64b imms as it generates more efficient code arc64: Update rtx_costs factoring in mode size arc64: Update add/sub with carry instructions arc64: Add {add, sub, neg, mult} overflow patterns arcXX: Fix overflow for mpy's arc64: Add SETcc.f instruction. arc64: Update alignments, add malloc alignment Revert "arc64: Update alignments, add malloc alignment" [arc32] Initial commit [arc32] iterate the call_insn [arc32] iterate the sibcall_insn [arc32] parameterise stack and parm boundaries [arc32] pass "-mcpu=arc32" to gas arc32: Update call templates for 32 bit arc32: Disable 64bit instructions when 32bit arcxx: Enable BI/BIH instructions by default arc32: Changes to libgcc arc32: Add CRT_CALL_STATIC 32b variant arc32: Update MOVE_MAX and handling of const(...) printing arc32: Use ti emulation only for arc64 builds [arc32] Disable muldi3_highpart [arc32] Add m32 flag to multilib [arc32] Merge <optab> modes to cover DImode correctly [arc32] Enable PC relative moves arc32: Protect EPI iterator in 32b mode [arc32] Trampoline generation handles 32 and 64 bits arc32: Use "plt" iso "plt34" for addressing arc64: Generalize split of double moves arc32: Select the right emulation for 32b arc32: Fix printing float numbers arcv3: Use UNITS_PER_LIMM macro for FPU arc32/dg.exp: Fix stack-usage-1 arc32: Add "-mll64" option arc32: Disable "TARGET_LL64" when target isn't 32-bit arc32: Introduce 64b double move splits arc32: Update BIGGEST_ALIGNMENT. arc32: Fix split double move arcXX: Add mpyf test for flags update arcXX: Consider the element of COMPLEX for reference pass check arc32: Add -mcpu=hs{5,6}x option instead of -m{32,64} arc32: Add new ARCv3:32 triplet arcXX: Fix warning. arc64: Linux target is defaulting to 64bit arches arc64: Cleanup rotate patterns arc64: enable simple cc-reg mods arc32: skip compile.exp=20000804-1.c arc64: Don't use vadd2h as 16b scalar op arc64: Update sched handling of acc regs. Add extra peephole step. arc64: Add NAKED attribute arc64: Add INTERRUPT attribute arc64: Honor memory models for BL instructions. arc64: Change modifier %h to %H, and %H to %V arc64: Add BRcc support, peephole2 tier. arc64: Update BRcc implementation. arc64: Update rtx costs (16b) arc32: Update LARGE memory model for HS5x arc64: Update specific tests to work for HS5x arc32: Honor large memory model for calls arc64: Update predicated execution patterns. Disable BBITx gen. arc64: Don't use pc-rel access for local symbols. arc64: Update 64bit add/sub instructions, when 32b used, carry operations are generated. arc64: Fix mpy snafu arc64: Enable unaligned access for linux toolchain arc32: add lnx target triplet arc32: add thread_pointer builtin arc32: add tls offset arc32: temporary fix for PIC symbols arc32: fix libgcc config entry for hs5x arc32: Update msimd option for HS5x CPUs arc64: Don't allow const into mov operands arc64: Update legitimate CONSTANT hook. Update movsi pattern. arc64: Add zeroextend patterns for add[123],asl,asr, and lsr arc64: Force any symbol out of the constant pool. arc64: Don't allow symbols as constants when PIC arc32: Allow 64b moves only when we have LL64 arc32: Update ldd/std mod letters. arc32: Enable DBNZ for ARCv3/32 arcv3: update legitimate_address_1_p() to cover ldd arcv3: adapt {restore,save}_callee_*() for ldd/std arc64: Add zero-extend xbfu arc32: Add "ldd/std" support arc32: Fix address scaling for double loads/stores arcXX: Fix saving/restoring callee saved registers for double loads/stores arc32: Enable 64b integer SIMD moves arc64: Scalled offsets for double access addresses needs to be smaller than s9 field arc32: Enable dot_prod4hi pattern. arc64: Set schedule issue rate to 2 arc32:multilib: Update cpu list with hs68 and hs58 arc64: Update scaling tests arc64: Fix double move spliting snafu arc64: Update vect_perm cost. arc32: Update v4hi vector reduction pattern arc64: Make SIMD default for hs{5,6}8 ARC32: Fix vec wideining mult arc64: Add vec_init pattern for v2si and v4hi vectors arc64: Add predicated version for sign extend using ASR/ALR arc64: Add accelerated vector reduction expands arc64: Fix typo in {s,h,d}exch unspec names. arc64: Support permutation vectors using vfexch insn. arc64: Add support for VFUNPKL/VFUNPKM insns arc64: Add vshuf tests for Float16 arc64: Add support for FVPACKL/FVPACKM arc64: Add support for FVBFLYL/FVBFLYM arc64: Cleanup arc64_simd_unpk func. arc64: Add cadd90/cadd270 for FP vectors arc64: Add cadd90/cadd270 for v2hi and v2si vectors arc64: Fix predicate pattern for mulhisi arc64: Add vpack2h shuffle patterns arc32: Fix vec_pack_trunc snafu arc64: Add v2hi init pattern. Not yet enabled arc64: Add vmax2/vmin2 instructions. arc64: Update vmax/vmin patterns arc64: Update unspec patterns arc64: Add combiner pattern for vpack2hl arc64: Add more vpack4hl shuffle patterns arc64: Enable movcc and cbranchcc instructions arc64: Add negcc and notcc patterns arc64: fix negl snafu arc64: Update notcc negcc patterns arc64: Optimize cmov pattern arc64: Update conditional mov patterns for FP modes arc64: Add reloads for cnot/cneg arc64: Cleanup md iterators arc64: Add DWARF2 alternate CFA column. arc64: Fix DWARF2 alternate CFA column patch arc64: Add an extra option to disable the vpack2h instructions. arc64: Update mov.f pattern arc64: Add fp-vector reverse shuffle arc64: Add combiner pattern for vpack2wl arc32: Add vect shifts for v2si arcv3: Add the option to use FPRs for memory options arc32: Adjust offset only when offset is positive arc64: Add config support for --with-cpu=... arc64: Update printing name of regs in ASM prologue arc64: Update FP-ABI: all record types are passed via R-regs arc64: Improve printing info about function frame arc64: fix sanfu arc64: unsigned max/min ops are synthesized using movcc, compare operands can be two non-regs, fix it arc64: Update compare test arc64: Remove F16_ADD_IMM instructions arc64: Chance fld128/fst128 to fldd64/fstd64 arc64: Guard remaining VPACK instructions arc64: Update required by gcc12 arc64: Allow VPACK* insn with msimd opt arc64: Update sth w6 instruction matching constraint arc64: Add brgt,brhi,brle and brls instructions Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The "getentropy" and "arc4random" check may not yield a correct result for the cross compile builds because linking is often not available for them and the C library headers (notoriously, newlib) may still declare these function prototypes even if they are not actually part of the final library -- for this reason, this commit disables the "getentropy" and "arc4random" checks for non-native builds. This effectively prevents the std::random_device from making use of these functions when `--with-newlib` is specified, which is indeed a correct behaviour because the newlib does not provide a default stub for the "getentropy" function (also note that the newlib "arc4random" implementation internally calls the missing "getentropy" function). For other C libraries, the `GLIBCXX_CROSSCONFIG` function may hard-code the availability of these functions by manually defining `HAVE_GETENTROPY` and `HAVE_ARC4RANDOM`, or by calling the `GLIBCXX_CHECK_GETENTROPY` and `GLIBCXX_CHECK_ARC4RANDOM` functions. libstdc++-v3: * configure.ac: Relocate GLIBCXX_CHECK_GETENTROPY and GLIBCXX_CHECK_ARC4RANDOM * configure: Regenerate. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The enter pattern instruction contains the necessary information for the dwarf machinery to generate the appropriate dwarf code. This patch is fixing the register offsets related to CFA, and adds a test. gcc/ * config/arc/arc.cc (arc_save_callee_enter): Use negative offsets. gcc/testsuite * gcc.target/arc/enter-dw2-1.c: New file. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
This commit updates the Zephyr RISC-V multilib configurations to explicitly specify `mcmodel=medany` when building the RV64 multilibs because the GCC defaults to the `medlow` code model when the `mcmodel` flag is not specified. Note that the Zephyr build system builds the RV64 targets using the `medany` code model because Zephyr uses the "flat" memory model and the addressing capabilities of the `medlow` model is too limited for it. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the multilib configurations such that the multilibs that are built for the `medany` code model are used when the `mcmodel` flag is not explicitly specified (i.e. when `medlow` code model is in use). Note that the multilibs compiled with the `medany` code model can be used with the application code compiled with the `medlow` code model. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This reverts the commit fb0746f because it causes the "GOT indirections," which require the final image to include the Global Offset Table (GOT), to be emitted for weak symbol references even when not building position-independent code or position-independent executable (i.e. when `-fno-pic` and `-fno-pie` parameters are specified). Before reverting this commit (GCC 12.1): adrp x0, :got:pm_state_exit_post_ops ldr x0, [x0, :got_lo12:pm_state_exit_post_ops] After reverting this commit (before GCC 12.1): adrp x0, .LC0 ldr x0, [x0, #:lo12:.LC0] ... .LC0: .xword pm_state_exit_post_ops Although the linker populates the Global Offset Table with the symbol addresses at the default linking address, which should be valid without any relocations in case of Zephyr because the Zephyr image is always loaded at a fixed address, this is far from ideal because the purpose of the Global Offset Table is to facilitate relocations and it comes with some overheads resulting in a minor footprint increase. For more details, refer to the following GitHub issue: zephyrproject-rtos/sdk-ng#547. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add mtune and mcpu options for ARCHS release 310a type CPU. The mtune=release31a is designed to be used as an alternative to the mcpu=hs4x_rel31 option. ARCHS4x release 31a uses DSP instructions which are implemented a bit different than mpy9. Hence, use safer mpy2 option. gcc/ * config/arc/arc-arch.h (arc_tune_attr): Add ARC_TUNE_ARCHS4X_REL31A variant. * config/arc/arc.cc (arc_override_options): Tune options for release 310a. (arc_sched_issue_rate): Use correct enum. (arc600_corereg_hazard): Textual change. (arc_hazard): Add release 310a tunning. * config/arc/arc.md (tune): Update and take into consideration new tune option. (tune_dspmpy): Likewise. (tune_store): New attribute. * config/arc/arc.opt (mtune): New tune option. * config/arc/arcHS4x.md (hs4x_brcc0, hs4x_brcc1): New cpu units. (hs4x_brcc_op): New instruction rezervation. (hs4x_data_store_1_op): Likewise. * config/arc/arc-cpus.def (hs4x_rel31): New cpu variant. * config/arc/arc-tables.opt: Regenerate. * config/arc/t-multilib: Likewise. * doc/invoke.texi (ARC): Update mcpu and tune sections. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
This adds a multilib alias for rv32iafc that reuses the libraries for rv32i. This is useful for IT8xxx2, which has a FPU but cannot use the -M extension. Signed-off-by: Peter Marheine <pmarheine@chromium.org>
This commit adds a new "base" multilib variant, rv32if/ilp32f, that can be used across the rv32i*f*/ilp32f targets, including rv32iafc/ilp32f. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
…unction as the existing implementation is buggy
The C99 math functions in the <cmath> header file are declared if and only if the `_GLIBCXX_USE_C99_MATH_TR1` is defined, whose autoconf check, `glibcxx_cv_c99_math_tr1`, requires all C99 math functions, including the `long double` math functions, to be available. Some C library implementations (for instance, newlib) may omit the C99 long double math function support when the type of `long double` is different from the type of `double` and, in such cases, the <cmath> header file ends up omitting the entirety of the C99 math functions. This commit reworks the `glibcxx_cv_c99_math_tr1` check such that it only tests the non-`long double` math functions, and adds a new check, `glibcxx_cv_c99_math_long_double`, that tests the `long double` math functions and defines `_GLIBCXX_USE_C99_MATH_LONG_DOUBLE_FUNCS` when these functions are available; which is then used by the <cmath> header file to conditionally import the C99 `long double` math functions, effectively making the C99 long double math function support in <cmath> an optional feature. libstdc++-v3/ChangeLog: * acinclude.m4 (_GLIBCXX_USE_C99_MATH_LONG_DOUBLE_FUNCS): New macro. (_GLIBCXX_USE_C99_MATH_TR1): Remove long double function tests. * config.h.in: Regenerate. * configure: Regenerate. * include/c_global/cmath: Use _GLIBCXX_USE_C99_MATH_LONG_DOUBLE_FUNCS. * include/tr1/cmath: Likewise. Signed-off-by: Stephanos Ioannidis <root@stephanos.io> Upstream-Status: Inappropriate [non-standard]
The problem here was a disconnect between splittable_const_int_operand predicate and the function riscv_build_integer_1 for 32bits with zbs enabled. The splittable_const_int_operand predicate had a check for TARGET_64BIT which was not needed so this patch removed it. Committed as obvious after a build for risc32-elf configured with --with-arch=rv32imac_zba_zbb_zbc_zbs. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/predicates.md (splittable_const_int_operand): Remove the check for TARGET_64BIT for single bit const values. (cherry picked from commit ffe4f55) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The problem here is the bswap<mode>2 pattern had a check for TARGET_64BIT but then used the X iterator. Since the X iterator is either SI or DI depending on the setting TARGET_64BIT, there is no reason for the TARGET_64BIT. OK? Built and tested on both riscv32-linux-gnu and riscv64-linux-gnu. Thanks, Andrew Pinski gcc/ChangeLog: PR target/106600 * config/riscv/bitmanip.md (bswap<mode>2): Remove condition on TARGET_64BIT as X is already conditional there. gcc/testsuite/ChangeLog: PR target/106600 * gcc.target/riscv/zbb_32_bswap-1.c: New test. * gcc.target/riscv/zbb_bswap-1.c: New test. (cherry picked from commit cb2daf5) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
…enabled The default expansion for bswap16 is two extractions (shift/and) followed by an insertation (ior) and then a zero extend. This can be improved with ZBB enabled to just full byteswap followed by a (logical) shift right. This patch adds a new pattern for this which does that. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu. gcc/ChangeLog: PR target/106601 * config/riscv/bitmanip.md (bswaphi2): New pattern. gcc/testsuite/ChangeLog: PR target/106601 * gcc.target/riscv/zbb_32_bswap-2.c: New test. * gcc.target/riscv/zbb_bswap-2.c: New test. (cherry picked from commit e5e6983) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
…BB enabled by default While looking for testcases to quickly test, I Noticed that check_effective_target_bswap was not enabled for riscv when ZBB is enabled. This patch checks if ZBB is enabled when targeting RISCV* for bswap. OK? Ran the testsuite for riscv32-linux-gnu both with and without ZBB enabled. PR testsuite/106690 gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_bswap): Return true if riscv and ZBB ISA extension is enabled. (cherry picked from commit dec5faa) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The problem here is two fold. With RISCV32, 32bit const_int are always signed extended to 64bit in HWI. So that means for SINGLE_BIT_MASK_OPERAND, it should mask off the upper bits to see it is a single bit for !TARGET_64BIT. Plus there are a few locations which forget to call trunc_int_for_mode when generating a SImode constant so they are not sign extended correctly for HWI. The predicates single_bit_mask_operand and not_single_bit_mask_operand need get the same handling as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with --with-arch=rvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or 64. Thanks, Andrew Pinski gcc/ChangeLog: PR target/106586 * config/riscv/predicates.md (single_bit_mask_operand): Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi. (not_single_bit_mask_operand): Likewise. * config/riscv/riscv.cc (riscv_build_integer_1): Don't special case 1<<31 for 32bits as it is already handled. Call trunc_int_for_mode on the upper part after the subtraction. (riscv_move_integer): Call trunc_int_for_mode before generating the integer just make sure the constant has been sign extended corectly. (riscv_emit_int_compare): Call trunc_int_for_mode after doing the addition for the new rhs. * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT, then mask off the upper 32bits of the HWI as it will be sign extended. (cherry picked from commit 2c721ea) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This patch surrounds the scalar operand of the MVE vcmp patterns with a vec_duplicate to ensure both operands of the comparision operator have the same (vector) mode. gcc/ChangeLog: PR target/107987 * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>, @mve_vcmp<mve_cmp_op>q_n_f<mode>): Apply vec_duplicate to scalar operand. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/pr107987.c: New test. (cherry picked from commit ed34c3b) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Newlib supports the aligned_alloc function (as well as memalign), define HAVE_ALIGNED_ALLOC so that libstdc++ will prefer the C standard function over the obsolete and non-standard memalign function. Signed-off-by: Keith Packard <keithp@keithp.com>
jwakely
reviewed
Jun 25, 2024
| @@ -357,6 +357,7 @@ else | |||
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| AC_DEFINE(HAVE_ICONV) | |||
| AC_DEFINE(HAVE_MEMALIGN) | |||
| AC_DEFINE(HAVE_ALIGNED_ALLOC) | |||
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Do you want to submit this part upstream? I don't think it was ever proposed.
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Newlib defines both of these names, but we prefer to use the standard C library function, aligned_alloc, over the non-standard (and obsolete) memalign.