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1. 5_Stage_Pipeline_RISCV_Processor 5_Stage_Pipeline_RISCV_Processor Public

   This Project describes a classic 5-stage Pipeline RISC-V Processor with Hazard Detection and Basic vector arithmetic features, made entirely using Verilog HDL.

   Verilog 5

2. RISC-V_CPU_Core RISC-V_CPU_Core Public

   This repository contains the working developer code for a RISC-V_CPU_Core made using TL-Verilog , Makerchip IDE, Sandpiper and Verilator.

   Verilog

3. sootty sootty Public

   Forked from Ben1152000/sootty

   A command-line tool for displaying vcd waveforms.

   Python

4. Single_Cycle_MIPS_Processor Single_Cycle_MIPS_Processor Public

   This repository contains the Complete implementation of the Single Cycle MIPS processor using Verilog. The processor supports R-type, I-type, and J-type instructions. The working and waveforms has …

   Verilog

5. Hacktoberfest-Data-Structure-and-Algorithms Hacktoberfest-Data-Structure-and-Algorithms Public

   Forked from BaReinhard/Hacktoberfest-Data-Structure-and-Algorithms

   A repo to contains data structure s and algorithms, regardless of language.

   Java

6. Twiggecode/Integer-Sequences Twiggecode/Integer-Sequences Public

   A database of algorithms of notable integer sequences. Easy for beginners to contribute.

   Python 41 118