riscv: alternative only works on !XIP_KERNEL

The alternative mechanism needs runtime code patching, it can't work on XIP_KERNEL. And the errata workarounds are implemented via the alternative mechanism. So add !XIP_KERNEL dependency for alternative and erratas. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Fixes: 44c9225 ("RISC-V: enable XIP") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
ginkage · Mar 10, 2022 · c80ee64 · c80ee64
1 parent 74583f1
commit c80ee64
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diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
@@ -2,6 +2,7 @@ menu "CPU errata selection"
 
 config RISCV_ERRATA_ALTERNATIVE
  bool "RISC-V alternative scheme"
+ depends on !XIP_KERNEL
  default y
  help
  This Kconfig allows the kernel to automatically patch the

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
@@ -14,8 +14,8 @@ config SOC_SIFIVE
  select CLK_SIFIVE
  select CLK_SIFIVE_PRCI
  select SIFIVE_PLIC
- select RISCV_ERRATA_ALTERNATIVE
- select ERRATA_SIFIVE
+ select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL
+ select ERRATA_SIFIVE if !XIP_KERNEL
  help
  This enables support for SiFive SoC platform hardware.