alx: extend data structures for multi queue support

Extend the driver data structures to be able to handle multiple queues.

Based on the downstream driver at github.com/qca/alx

Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

drivers/net/ethernet/atheros/alx/alx.h

@@ -50,6 +50,10 @@ struct alx_buffer {
 };
 
 struct alx_rx_queue {
+ struct net_device *netdev;
+ struct device *dev;
+ struct alx_napi *np;
+
  struct alx_rrd *rrd;
  dma_addr_t rrd_dma;
 
@@ -58,16 +62,26 @@ struct alx_rx_queue {
 
  struct alx_buffer *bufs;
 
+ u16 count;
  u16 write_idx, read_idx;
  u16 rrd_read_idx;
+ u16 queue_idx;
 };
 #define ALX_RX_ALLOC_THRESH 32
 
 struct alx_tx_queue {
+ struct net_device *netdev;
+ struct device *dev;
+
  struct alx_txd *tpd;
  dma_addr_t tpd_dma;
+
  struct alx_buffer *bufs;
+
+ u16 count;
  u16 write_idx, read_idx;
+ u16 queue_idx;
+ u16 p_reg, c_reg;
 };
 
 #define ALX_DEFAULT_TX_WORK 128
@@ -76,6 +90,18 @@ enum alx_device_quirks {
  ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG = BIT(0),
 };
 
+struct alx_napi {
+ struct napi_struct napi;
+ struct alx_priv *alx;
+ struct alx_rx_queue *rxq;
+ struct alx_tx_queue *txq;
+ int vec_idx;
+ u32 vec_mask;
+ char irq_lbl[IFNAMSIZ + 8];
+};
+
+#define ALX_MAX_NAPIS 8
+
 #define ALX_FLAG_USING_MSIX BIT(0)
 #define ALX_FLAG_USING_MSI BIT(1)
 
@@ -96,6 +122,11 @@ struct alx_priv {
  unsigned int size;
  } descmem;
 
+ struct alx_napi *qnapi[ALX_MAX_NAPIS];
+ int num_txq;
+ int num_rxq;
+ int num_napi;
+
  /* protect int_mask updates */
  spinlock_t irq_lock;
  u32 int_mask;