modules/zstd/memory: Add MemWriter

Internal-tag: [#65205] Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
google · Sep 23, 2024 · 6339ac1 · 6339ac1
1 parent b62f727
commit 6339ac1
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diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD
@@ -598,3 +598,78 @@ place_and_route(
     tags = ["manual"],
     target_die_utilization_percentage = "10",
 )
+
+xls_dslx_library(
+    name = "mem_writer_dslx",
+    srcs = ["mem_writer.x"],
+    deps = [
+        ":axi_dslx",
+        ":axi_st_dslx",
+        ":axi_stream_add_empty_dslx",
+        ":axi_writer_dslx",
+        ":common_dslx",
+    ],
+)
+
+xls_dslx_test(
+    name = "mem_writer_dslx_test",
+    library = ":mem_writer_dslx",
+)
+
+mem_writer_codegen_args = common_codegen_args | {
+    "module_name": "mem_writer",
+    "pipeline_stages": "2",
+    "streaming_channel_data_suffix": "_data",
+    "multi_proc": "true",
+    "flop_inputs_kind": "skid",
+    "flop_outputs_kind": "skid",
+    "worst_case_throughput": "1",
+}
+
+xls_dslx_verilog(
+    name = "mem_writer_verilog",
+    codegen_args = mem_writer_codegen_args,
+    dslx_top = "MemWriterInst",
+    library = ":mem_writer_dslx",
+    opt_ir_args = {
+        "top": "__mem_writer__MemWriterInst__MemWriter_0__16_32_4_2_4_4_2_next",
+    },
+    tags = ["manual"],
+    verilog_file = "mem_writer.v",
+)
+
+verilog_library(
+    name = "mem_writer_verilog_lib",
+    srcs = [
+        ":mem_writer.v",
+    ],
+    tags = ["manual"],
+)
+
+synthesize_rtl(
+    name = "mem_writer_synth_asap7",
+    standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
+    tags = ["manual"],
+    top_module = "mem_writer",
+    deps = [
+        ":mem_writer_verilog_lib",
+    ],
+)
+
+benchmark_synth(
+    name = "mem_writer_benchmark_synth",
+    synth_target = ":mem_writer_synth_asap7",
+    tags = ["manual"],
+)
+
+place_and_route(
+    name = "mem_writer_place_and_route",
+    clock_period = CLOCK_PERIOD_PS,
+    core_padding_microns = 2,
+    min_pin_distance = "0.5",
+    placement_density = "0.30",
+    stop_after_step = "global_routing",
+    synthesized_rtl = ":mem_writer_synth_asap7",
+    tags = ["manual"],
+    target_die_utilization_percentage = "10",
+)