modules/zstd: Add FSE probability frequency decoder

Internal-tag: [#55149]
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>

xls/modules/zstd/BUILD

@@ -20,6 +20,7 @@ load("@rules_hdl//verilog:providers.bzl", "verilog_library")
 load(
     "//xls/build_rules:xls_build_defs.bzl",
     "xls_benchmark_ir",
+    "xls_benchmark_verilog",
     "xls_dslx_library",
     "xls_dslx_test",
     "xls_dslx_verilog",
@@ -677,3 +678,98 @@ xls_dslx_test(
     },
     library = ":shift_buffer_dslx",
 )
+
+xls_dslx_library(
+    name = "fse_proba_freq_dec_dslx",
+    srcs = ["fse_proba_freq_dec.x"],
+    deps = [
+        ":common_dslx",
+        ":shift_buffer_dslx",
+        "//xls/examples:ram_dslx",
+    ],
+)
+
+xls_dslx_test(
+    name = "fse_proba_freq_dec_dslx_test",
+    dslx_test_args = {"compare": "none"},
+    library = ":fse_proba_freq_dec_dslx",
+)
+
+xls_dslx_verilog(
+    name = "fse_proba_freq_dec_verilog",
+    codegen_args = {
+        "module_name": "fse_proba_freq_dec_dslx",
+        "generator": "pipeline",
+        "delay_model": "asap7",
+        "ram_configurations": "ram:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format(
+            latency = 5,
+            rd_req = "fse_proba_freq_dec__rd_req_s",
+            rd_resp = "fse_proba_freq_dec__rd_resp_r",
+            wr_req = "fse_proba_freq_dec__wr_req_s",
+            wr_resp = "fse_proba_freq_dec__wr_resp_r",
+        ),
+        "pipeline_stages": "6",
+        "reset": "rst",
+        "reset_data_path": "true",
+        "reset_active_low": "false",
+        "reset_asynchronous": "true",
+        "flop_inputs": "false",
+        "flop_single_value_channels": "false",
+        "flop_outputs": "false",
+        "worst_case_throughput": "1",
+        "use_system_verilog": "false",
+    },
+    dslx_top = "FSEProbaFreqDecoderInst",
+    library = ":fse_proba_freq_dec_dslx",
+    opt_ir_args = {
+        "inline_procs": "true",
+        "top": "__fse_proba_freq_dec__FSEProbaFreqDecoderInst__FSEProbaFreqDecoder_0__64_32_8_10_1_256_10_next",
+    },
+    verilog_file = "fse.v",
+)
+
+xls_benchmark_ir(
+    name = "fse_proba_freq_dec_ir_benchmark",
+    src = ":fse_proba_freq_dec_verilog.opt.ir",
+    benchmark_ir_args = {
+        "pipeline_stages": "6",
+        "delay_model": "asap7",
+    },
+)
+
+xls_benchmark_verilog(
+    name = "fse_proba_freq_dec_verilog_benchmark",
+    verilog_target = "fse_proba_freq_dec_verilog",
+)
+
+verilog_library(
+    name = "fse_proba_freq_dec_lib",
+    srcs = [
+        ":fse_proba_freq_dec.v",
+    ],
+)
+
+synthesize_rtl(
+    name = "fse_proba_freq_dec_asap7",
+    standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
+    top_module = "fse_proba_freq_dec",
+    deps = [
+        ":fse_proba_freq_dec_lib",
+    ],
+)
+
+benchmark_synth(
+    name = "fse_proba_freq_dec_benchmark_synth",
+    synth_target = ":fse_proba_freq_dec_asap7",
+)
+
+place_and_route(
+    name = "fse_proba_freq_dec_place_and_route",
+    clock_period = "750",
+    core_padding_microns = 2,
+    min_pin_distance = "0.5",
+    placement_density = "0.30",
+    skip_detailed_routing = True,
+    synthesized_rtl = ":fse_proba_freq_dec_asap7",
+    target_die_utilization_percentage = "10",
+)

xls/modules/zstd/common.x

@@ -16,9 +16,12 @@ pub const DATA_WIDTH = u32:64;
 pub const MAX_ID = u32::MAX;
 pub const SYMBOL_WIDTH = u32:8;
 pub const BLOCK_SIZE_WIDTH = u32:21;
+pub const BLOCK_PACKET_WIDTH = u32:32;
+pub const FSE_MAX_SYMBOLS = u32:256;
+pub const FSE_MAX_ACCURACY_LOG = u32:9;
 
 pub type BlockData = bits[DATA_WIDTH];
-pub type BlockPacketLength = u32;
+pub type BlockPacketLength = bits[BLOCK_PACKET_WIDTH];
 pub type BlockSize = bits[BLOCK_SIZE_WIDTH];
 pub type CopyOrMatchContent = BlockData;
 pub type CopyOrMatchLength = u64;
@@ -54,3 +57,30 @@ pub struct SequenceExecutorPacket {
     content: CopyOrMatchContent, // Literal data or match offset
     last: bool, // Last packet in frame
 }
+
+pub enum CompressionMode : u2 {
+    PredefinedMode    = 0,
+    RLEMode           = 1,
+    FSECompressedMode = 2,
+    RepeatMode        = 3,
+}
+
+pub struct SequenceConf {
+    sequence_count: u17,
+    literals_mode: CompressionMode,
+    offset_mode: CompressionMode,
+    match_mode: CompressionMode,
+}
+
+pub struct SequencePathCtrl {
+    literals_count: u20,
+    last_block: bool,
+    id: u32,
+    sequence_conf: SequenceConf,
+}
+
+pub struct SequenceData {
+    bytes: bits[64],
+    length: u32,
+    last: bool,
+}